Page Content

• Location

• Introduction

• Circuit Description

• Demonstration and Simulation

• Results

• Real-time Performance

• References

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Location

This example model can be found in the MMC installation under the directory of /Examples/MMC_STATCOM

Introduction

This demo simulates the MMC STATCOM model. MMC model can be implemented in CPU or in FPGA. In the CPU implementation, the MMC can be modeled in detailed Switching Function (SWF) and Average (AVM) Models, while in FPGA implementation, only a detailed SWF model is available. The selection of CPU and FPGA is defined in the initialization file (init_MMC_STATCOM.m) included in the same folder of the Simulink file. Based on the type of study, the users can choose CPU or FPGA model type. Users should change the model type from one to another before running the simulation by uncommenting the appropriate model selection for each MMC in the initialization file.

This demo of full bridge MMC STATCOM is modeled using the RT-Lab MMCValves Block, which can be used for half-bridge, full-bridge, clamp-double and T-type MMC cells. The demo shows the model can simulate either off-line with much faster simulation speed comparing to other offline simulation software, or in real-time. A full-bridge MMC cell consists of a dc capacitor, a discharge resistor, and four power electronic switches.

The MMC block models up to a maximum of 50 individual MMC SMs per valve in the CPU implementation. Multiple MMC blocks can be piled up to model an MMC valve of more than 50 SMs, however, this will limit the performance in real-time, and thus for models with more than 50 SMs per valve, it is recommended to use the FPGA implementation. In the FPGA mode of operation, the number of SMs is limited by the user license. In the standard firmware, the FPGA model supports up to 511 SMs per valve, more can be added upon request.

Moreover, the MMC block has the following features. More details and features are presented in the overview of the MMC Valves library.

• The values of cell capacitances and the discharge resistance can be adjusted during simulation.

• There is a dead time between each pair of upper and lower gates.

• Temporary or permanent short circuit of cell capacitor in any cell can be simulated.

• There are normal mode and debugging mode. In the debugging mode, the capacitor voltages can be set to an average value (to temporarily replace voltage balance control) or a fixed value.

The demo is structured in two main sub-systems:

SC_Console: Is the console subsystem. Contains the displays, constant blocks, and parameter blocks to interact with the model when it is running. In the console, the power references can be set and the simulation waveforms are displayed in scopes. The console includes also the MMC Valves parameter blocks to set some of the parameters to the MMCs in the simulation.

SM_sys: Contains control (high-level control) and plant (MMC-based STATCOM) model. In the STATCOM model, the different electrical elements (transformer, breakers, fault, AC grid) are included and also the MMC Valves block that implements the model of the MMC. The low-level control of this MMC-based STATCOM is also included in the corresponding MMC Valves Low-Level block.

The STATCOM model is composed of MMCValvesParam and MMCValves Block, please refer to the help file for more information on setting relevant parameters. The MMC block is used to represent the behavior of a valve circuit based on the calculations from MMCValvesParam Configuration block.

The signal interactions between the valve and the calculation block are done internally. In this demo, only 3 valves are presented in the model following the structure of MMC STATCOM.

Circuit Description

The MMC STATCOM is studied in a test system as in the figures below. The test system parameters are given in TABLE I. There is a 100 MVA load at the bus of point of common coupling (PCC) with a power factor of 0.95. The short circuit ratio (SCR) at PCC is approximately 4, which means the STATCOM has a weak connection to the grid. The STATCOM parameter is given in TABLE II. The carrier signal has a low frequency, i.e. 5 times the line frequency. The arm inductor has a value of 0.1 p.u.

Note: In this demo model the STATCOM is connected in star and the same model can also used in a delta connection. However, the user needs to change the connections of the STATCOM from star to delta.

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Demonstration and Simulation

Various phenomena can be studied using the MMC STATCOM model. In this demo model, four scenarios, i.e., the steady state, voltage sag, 3-phase-ground AC fault, and SM capacitor DC fault, can be studied and the results are presented in the reference paper [1]. The model can be controlled and simulation results can be monitored during simulation in the console subsystem.

For the control:

• para is to set the MMC parameters.

• load shed is to connect to (=1) or shed (=0) the load.

• ac no_fault is to set a 0.05sec (adjustable in the model) 3-phase-ground fault at PCC.

• voltage sag is to set voltage sag at the source bus (0 for no sag, and 0.1 for 0.1 pu voltage sag).

• ctrl mode sets the STATCOM either in voltage mode or Q mode. The voltage mode controls the voltage at PCC to 1 p.u. as long as reactive power allows. The Q mode controls the reactive power to the set value set at the q_ref.

Note: after starting the simulation, the "Enable pulse" checkbox inside the MMC (CPU or FPGA) parameters block should be checked in order to enable STATCOM's operation.

For the monitoring:

The first scope "ScopeMeas" displays respectively from the topmost to the lowermost sub-scopes:

1. 4 signals, i.e. STATCOM voltages in phases a, b, c, and neutral.

2. 4 signals, i.e. the maximum, minimum, average of all capacitor voltage and the value of the 1st cell.

3. 3 signals, i.e. average capacitor voltage of phases a, b, and c.

4. 3 signals, i.e. source bus voltages in phases a, b, and c.

5. 3-phase voltages at PCC.

6. 3 phase currents at PCC.

7. 3-phase active and reactive powers at PCC.

Notes for FPGA implementation:

For real-time simulation in an FPGA type of model ensure the appropriate Board ID and bitstream file have been chosen. The user can set these details for MMC inside the subsystem “Lib_MMC_cpu_STATCOM/SM_sys/Plant/MMCSTATCOMModel/Model/MMCinFPGA”. Inside these subsystems, the user can find the OpCtrl (or OpLnk) block where the Board ID and bitstream filenames must be set as shown in below figure.

Further, in RT-LAB under the Execution tab, the Real-Time simulation mode has to be set before building the model. If the model type is CPU the user must use “Software Synchronization”, whereas in FPGA type model, this need to be changed to “Hardware synchronized”, as shown in the below figure.

Results

Out of the above-discussed events, a voltage sag case study has been considered to showcase the response of the MMC STATCOM model. Above discussed controls are used to simulate the voltage sag event and the signals discussed above are monitored. The model is simulated offline to showcase the response of the CPU SWF model of STATCOM. However, one can run the model in real-time too.

Nearly, at a time, t=1.55 seconds, the pulses are enabled by checking the "Enable pulse" checkbox inside the MMCValvesParam parameters block. Immediately after and before pulses are enabled figure 1 shows the response of the system. At time, t is approximately at 2.75 seconds the voltage sag even is applied by toggling the switch from zero to one, whose response before and after voltage sag events are shown in figure 2. One can observe that to maintain the voltage at terminals the STATCOM increases its reactive power from 0 to 0.4 pu. Moreover, the overall response of the system is shown in Figure 3.

Real-time Performance

The model has been run on a dual-Xeon-based 3.466 GHz CPU with Red-hat operating system. The time-step is 20 µs, and 1 CPU core has been assigned. Note the time step is as short as 20 µs. The model can run in 2 modes, the CPU mode and the AVM mode. The real-time simulation performance will be different with the 2 modes.

With both converters running under the CPU mode, the performance is shown as follows:

With both converters running under the AVM mode, the performance is shown as follows:

References

1. Wei Li, L.-A. Gregoire, and Jean Belanger, "Modeling and Control of a Full-Bridge Modular Multilevel STATCOM," IEEE Power and Energy Society General Meeting, 2012, 7 pages.

2. W. Li et J. Belanger, “An equivalent circuit method for modelling and simulation of modular multilevel converters in real-time HIL test bench,” IEEE Transactions on Power Delivery, vol. 31, no. 15, pp. 240—2409, 2016.

3. W. Li, L. -A. Grégoire and J. Bélanger, "A Modular Multilevel Converter Pulse Generation and Capacitor Voltage Balance Method Optimized for FPGA Implementation," in IEEE Transactions on Industrial Electronics, vol. 62, no. 5, pp. 2859-2867, May 2015, doi: 10.1109/TIE.2014.2362879.

See Also

Overview of the MMC Valves Library, MMCValves Block, MMC Valves Parameters Block, MMC Valves Low Level Control Block, MMC CPU Parameter block, MMC CPU Model Configuration block, VSC Node block.