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OP5340 DB37F Pin Assignment
The following tables provide the general pin assignments for the OP5340 DB37 connectors.
Detailed pin assignments for all connectors can be found in the System Description document provided with your order, or refer to the general pin assignment of your specific unit.
Before designing cables, OPAL-RT recommends using the guideline Simulator EMC cable recommendations.
Group A and B - Connector P1 - Channel 00 to 15 (Connector P2 not used) |
 OP5340 DB37F Pin Assignment
| |||
|---|---|---|---|---|
DB37 Pin | Assignment | DB37 Pin | Assignment | |
1 | +AIN00 | 20 | -AIN00 | |
2 | +AIN01 | 21 | -AIN01 | |
3 | +AIN02 | 22 | -AIN02 | |
4 | +AIN03 | 23 | -AIN03 | |
5 | +AIN04 | 24 | -AIN04 | |
6 | +AIN05 | 25 | -AIN05 | |
7 | +AIN06 | 26 | -AIN06 | |
8 | +AIN07 | 27 | -AIN07 | |
9 | +AIN08 | 28 | -AIN08 | |
10 | +AIN09 | 29 | -AIN09 | |
11 | +AIN10 | 30 | -AIN10 | |
12 | +AIN11 | 31 | -AIN11 | |
13 | +AIN12 | 32 | -AIN12 | |
14 | +AIN13 | 33 | -AIN13 | |
15 | +AIN14 | 34 | -AIN14 | |
16 | +AIN15 | 35 | -AIN15 | |
17 | Refer to unit’s pin assignment* | 36 | Refer to unit’s pin assignment* | |
18 | Reserved | 37 | Reserved | |
19 | Refer to unit’s pin assignment* |
|
| |
* Unit can be a Real-time Simulator or an FPGA Processor and IO Expansion Unit from the OP4000 or the OP5000 series.
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