Implementation of MMC Model in CPU

• Useful for off‐line or accelerated simulation of a simple system (no FPGA needed) and algorithm development with SIMULINK
• Supporting MMC‐HB and MMC‐FB
• Unlimited number of SM per valve
• Several CPU cores are used to calculate the MMC and grid models
• 1 CPU can solve around 300 SM at a time step of 25μs
• Providing SM Vcap debugging mode to help user developing their controller

MMC CPU Model Features

The MMC block has following features:

• The values of cell capacitances and the discharge resistance can be adjusted during simulation.
• There is a dead‐time between each pair of upper and lower gates.
• Temporary or permanent short circuit of cell capacitor in any cells can be simulated.
• There are normal mode and debugging mode. In the debugging mode, the capacitor voltages can be set to average value (to temporarily replace voltage balance control) or a fixed value.

MMC CPU Parameters Block

The MMC parameter and mode are set in the “MMC para” block

• Cell capacitor in farads
• Discharging resistor in ohms
• If the cell short‐circuit are permanent (Vcap keeps zero after fault when checked) or recoverable (Vcap can be recharged when the fault is cleared when unchecked)
• Vcap mode
  
  • 0: normal operation
  • 1: Vcap reset to 0
  • 2: Vcap use average value
  • 3: Vcap reset to fix value
• Vcap fixed value when Vcap mode is 3 (Vcap reset to fix value)
• IGBT dead‐time. For example, if the simulation time step is 20 us and the dead time is 5 us, input 0.25 (= 5/20).

MMC Parameters Block

Parameters Tab

• Cell capacitance (farads): capacitance of each cell capacitor in Farad.
• Resistance in shunt with the cell capacitor (Ohms): define the value of resistance in shunt with the cell capacitor.
• Keep cell short‐circuit upon error: When it is checked, the short‐circuit fault is applied.

• Vcap mode: four operation mode options.
  
  • 0: normal operation
    
    • It determines how the cell capacitor voltage is calculated in the CPU. Always choose mode “0: normal” for normal operation mode, where the cell capacitor voltage respects physical law, i.e. determined by the charging current and capacitance.
  • 1: Vcap reset to 0
    
    • The other three modes are used to debug the controller. Note that the capacitor voltage may not follow physical law in any of the debug modes. In mode “1: Vcap reset to 0”, all cell capacitor voltages are forced to zero.
    • 
  • 2: Vcap use an average value
    
    • In mode “2: Vcap use average value”, all capacitor voltages are calculated by the charging current and capacitance, then the average value of each half arm is applied to all cell capacitors in that half arm. It emulates the performance when applying an ideal capacitor voltage balancing algorithm. This model is under debugging and will be provided in a future version.
    • 
  • 3: Vcap reset to fix value
    
    • In mode “3: Vcap reset to fix value”, all cell capacitor voltages are forced to a fixed value given in the next parameter “Vcap fix value (pu)”. This mode emulates the performance when applying an ideal capacitor voltage control.
    • 

MMC HS & CDSM CPU Block

• The MMC HB & CDSM block has 4 inputs, 2 outputs and 2 connection ports.
• The first 2 inputs are the two groups of gate signals. Each input has a dimension as the same as the number of cells in a valve. For example, if the valve has 30 cells, the 1st inputs are 30 G1 & G3 (for CDSM) gate signals, the 2nd inputs are 30 G2 & G4 (for CDSM) gate signals, etc.
• The 3rd input is MMC parameters and has a dimension of 5 signals. It is connected to the MMC parameter blocks explained in the previous slide.
• The 4th input is for G5, when the SM is CDSM, user can control it, otherwise it can be set as ‘1’ by default.
• The first output of the MMC block with the same dimension as the number of cells in a valve is individual capacitor voltages.
• The second output gives the MMC valve terminal current and voltage.
• The other connection ports are two terminals of the MMC valve.

MMC HB (CDSM) HVDC Demo

The demo MMC HVDC system as below.

The model can be controlled and the simulation results can be monitored during simulation in the console subsystem as below.

In the control

• Pref_left is the set point of the active power reference;
• Qref_left is the set point of the reactive power reference at Terminal 1;
• Pulse_ON_left is to enable or disable the PWM pulses of converter at Terminal 1;
• Qref_right is the set point of the reactive power reference at Terminal 2;
• Pulse_ON_right is to enable or disable the PWM pulses of converter at Terminal 2;
• MMC para is to set the MMC parameters which is explained in the previous section;
• data_logging is to start or stop data logging;
• dcbrk is to close or open the dc breaker;
• ac_brk@T1 is to cut in or bypass the charging resistor at Terminal 1.
• ac_brk@T2 is to cut in or bypass the charging resistor at Terminal 2.

For the monitoring

• The first scope “dc” displays respectively from the topmost to the lowermost sub‐scopes:
  
  • 2 signals, i.e. dc currents at positive and negative poles;
  • 3 signals, i.e. dc voltages of positive‐ground, negative‐ground, and positive‐negative at Terminal 1;
  • 3 signals, i.e. dc voltages of positive‐ground, negative‐ground, and positive‐negative at Terminal 2.
• The second scope “ac side” displays following signals from the topmost to the lowermost sub‐scopes respectively:
  
  • 3 phase voltages at Terminal 1;
  • 3 phase currents at Terminal 1;
  • 3‐phase active and reactive powers at Terminal 1;
  • 3 phase voltages at Terminal 2;
  • 3 phase currents at Terminal 2;
  • 3‐phase active and reactive powers at Terminal 2.
• The scope “MMC @T1” displays following signals for Terminal 1 from the topmost to the lowermost sub‐scopes respectively:
  
  • 6 MMC valve voltages;
  • 6 MMC valve currents;
  • 6 MMC cell capacitor average voltages at each valve;
  • 6 MMC valve voltage references from the control.
• The scope “MMC @T2” displays following signals for Terminal 1 from the topmost to the lowermost sub‐scopes respectively:
  
  • 6 MMC valve currents;
  • 6 MMC valve voltages;
• The two displays “Vcap@T1” and “Vcap@T2”, each gives 18 V_cap values. They are minimum, maximum, and average capacitor voltages of each valve (3*6) respectively.

Real‐time Performance

• The model has been run on a dual‐Xeon based 3.466 GHz CPU with Red‐hat operating system. The time‐step is 30 μs, and 3 CPU cores have been assigned. Note the time step is as short as 30 μs and the CPU usage for the power system simulation including the MMC is 63.52%.

Dc link open, Qref=0, Dc link open, Qref1=0.3, Qref2=‐0.2

Close dc link by setting <dcbrk> =1, change Pref and Qref.

Observe the Vcap and Vdc is controlled to 1 pu. P and Q follow their references.

DC link closed, Pref=0.4,Qref1=0.3,Qref2=‐0.2

MMC FB CPU Block

The MMC‐FB block has 5 inputs, 2 outputs, and 2 connection ports.

• The first 4 inputs are the four gate signals. Each input has a dimension same as the number of cells in a valve. For example, if the valve has 20 cells, the 1st inputs are 20 G1 signals, the 2nd inputs are 20 G2 signals, etc.
• The 5th input is MMC parameters and has a dimension of 5 signals. It is connected to the MMC parameter blocks explained in the previous slides.
• The first output of the MMC block with the same dimension as the number of cell in a valve is individual capacitor voltages.
• The second output gives the MMC valve terminal current and voltage.
• The other connection ports are two terminals of the MMC valve.

MMC FB STATCOM Demo

The demo MMC STATCOM system is as below.

System Parameters

MMC STATCOM Parameters

The model can be controlled and the simulation results can be monitored during simulation in the console subsystem as below.

For the control

• MMC para is to set the MMC parameters;
• pulse ON is to enable or disable the PWM pulses;
• load shed is to connect to (=1) or shed (=0) the load;
• ac no_fault is to set a 0.05sec (adjustable in the model) 3‐phase‐ground fault at PCC;
• voltage sag test2 is to set voltage sag at source bus (0 for no sag, and 0.1 for 0.1 pu voltage sag);
• ctrl mode set the STATCOM either in voltage mode or Q mode. The voltage mode controls the voltage at PCC to 1 p.u. as long as reactive power allows. The Q mode control the reactive power to the set value set at the q_ref.

For the monitoring

• The first scope “measscope” displays respectively from the topmost to the lowermost sub‐scopes:
  
  • 4 signals, i.e. the maximum, minimum, average of all capacitor voltage and the value of the 1st cell;
  • 3 signals, i.e. average capacitor voltage of phases a, b, and c;
  • 4 signals, i.e. STATCOM voltages in phases a, b, c, and neutral;
  • 3 signals, i.e. source bus voltages in phases a, b, and c;
• The second scope “VIPQ” displays following signals at the Bus PCC from the topmost to the lowermost sub‐scopes respectively,
  
  • 3 phase voltages;
  • 3 phase currents;
  • 3‐phase active and reactive powers.

Real‐time Performance

• The model has been run on a dual‐Xeon based 3.466 GHz CPU with Red‐hat operating system. The time‐step is 20 μs, and 3 CPU cores have been assigned. Note the time step is as short as 20 μs and the CPU usage for the power system simulation including the MMC STATCOM is 53.02%.

Load connected, no ac fault, no voltage sag, with voltage control

Load connected, no ac fault, 0.1 voltage sag, with voltage control