MMC demos are located in the folder:

C:\OPAL-RT\ MMC \%Version#%\Examples

Users can browse to the folder above, import the demo to a RTLAB project then compile and load the demo.

Unitary Test Model

• In the unitary test model, the MMC is not connected to grid. The valve current and gate signals can be manually set by user.
• The purposes of the unitary test model are to
  
  • test basic functions of MMC
  • validate the parameters of the model
  • help user better understand the model
• A few tests are listed in the presentation.

Unitary Test Model: Half-Bridge Topology

Test 1

• In the “MMC parameter” block, set < Vcap mode> to “fixed value”
• Change the Vcap fix value;
• In the Display “ vcap ” at console , user should see the capacitor voltage being the same as the set value.

Test 2 (Continue with Test 1)

• In the MMC parameters block/ fault tab, apply or clear fault on cells. Select “clear temporary fault (checked)” at MMC parameter block so fault can be cleared when change the ON and OFF signals of fault vectors
• In Display “ vcap ” at console, the corresponding Vcap reading should reflect if the cell has a short circult fault (Vcap = 0)
• Try unchecking clear temporary fault option.

Test 3 (Continue with Test 2)

• Clear all faults.
• In the “MMC parameter” block, set <MMC gating signal routing> to “0: internal” in operation tab and set <gating signal from> to  “1: embedded VBC in FPGA” in controller tab.
• Open the scope in console to see Vmmc follows reference.
  
  • Double click to open <ref> subsystem, one can change reference (magnitude, frequency, offset for sinusoidal or constant).

Test 4 (Continue with Test 3)

• In the “MMC parameter” block, set <gating signal from> to “0: gate signal from CPU” in controller tab.
• In <MMC pulse> block, change status of selected cells.
• Observe that Vmmc = <Nb. of ON cell> * Vcap

Test 5 (Continue with Test 4)

• If pulses Input is connected to external controller, in the “MMC parameter” block, set < MMC gating signal routing>to “1: external from SFP”
• Change status of cell from external control.
• Observe that Vmmc = <Nb. of ON cell> * Vcap

Test 6 (Continue with Test 4)

• in the “MMC parameter” block, set < Vcap mode> to “normal operation”, SM capacitor normal discharge resistor design value to a large value ( e.g.2.2Mohm)
• set <gating signal from>to “0: gate signal from CPU”, in <MMC pulse> block change status of
• Change arm current to 0.001, 0, or 0.001 constant.
• Observe Vcap of each cell either charges or stays constant or discharging depending on its status and arm current direction.

Test 7 (Continue with Test 6)

• Same test as Test 6 except that set <MMC gating signal routing>to “1: external from SFP” in operation tab.
• Change status of cells through IO and arm current direction.
• Observe Vcap of each cell either increase or decrease or keep constant according to its status and arm current direction

MMC HVDC Demo Model

• The MMC system demo model is to further test the MMC model by operating it in a power system.
• A 2 terminal MMC HVDC system is served for this purpose.
• In this model, one terminal (T1) is simulated using FPGA model and the other terminal (T2) is simulated using CPU model.
• The controller in this model is developed by OPALRT for demo purpose.

MMC HVDC Demo Model: Case Study

The demo MMC HVDC system as below.

MMC HDVC Demo Model: Task Mapping

For the control:

• Pref pu is the set point of the active power reference;
• Qref_T1 pu is the set point of the reactive power reference at Terminal 1;
• Pulse_ON_T1 is to enable or disable the PWM pulses of converter at Terminal 1;
• Qref_T2 pu is the set point of the reactive power reference at Terminal 2;
• Pulse_ON_T2 is to enable or disable the PWM pulses of converter at Terminal 2;
• data_logging is to start or stop data logging;
• dcbrk is to close or open the dc breaker;
• ac_brk@T1 is to cut in or bypass the charging resistor at Terminal 1;
• ac_brk@T2 is to cut in or bypass the charging resistor at Terminal 2;
• MMC parameters is to set the MMC parameters which is explained in the previous section
• Fault set is to set fault in specific patterns in designated valves;
• MMC pulse is to send gating signals from CPU to FPGA

For the monitoring:

• The first scope “dc” displays respectively from the topmost to the lowermost sub scopes:
  
  • 2 signals, i.e. dc currents at positive and negative poles;
  • 3 signals, i.e. dc voltages of positive ground, negative ground, and positive-negative at Terminal 1;
  • 3 signals, i.e. dc voltages of positive ground, negative ground, and positive-negative at Terminal 2.
• The second scope “ac side” displays following signals from the topmost to the lowermost sub scopes respectively:
  
  • 3 phase voltages at Terminal 1;
  • 3 phase currents at Terminal 1;
  • 3 phase active and reactive powers at Terminal 1;
  • 3 phase voltages at Terminal 2;
  • 3 phase currents at Terminal 2;
  • 3 phase active and reactive powers at Terminal 2.
• The scope “MMC ” displays following signals for Terminal 1 from the topmost to the lowermost sub scopes respectively:
  
  • 6 MMC valve voltages;
  • 6 MMC valve currents;
  • 6 MMC cell capacitor average voltages at each valve;
  • 6 MMC valve voltage references from the control.
• The scope “ Vcap ”
  
  • Capacitor voltages coming from FPGA (terminal 1), they are regrouped as 32x3 and 16x6 matrixes to display 192 values in total
• The scope “Display1” displays:
  
  • 3 capacitor voltages from terminal 2, they are minimum, maximum and selected capacitor voltages respectively.

Real-time Performance

• The model has been run on a dual Xeon based 3.466 GHz CPU with Redhat operating system in Hardware Synchronization Mode. The time step is 25 µs, and 4 CPU cores have been assigned. Note the time step is as short as 25 µs and the CPU usage for the power system simulation including the MMC is 46.21%.

• In the console,
  
  • <Pref pu > reference for active power
  • <Qref_T1 pu > reference for reactive power for Terminal 1
  • <Qref_T2 pu > reference for reactive power for Terminal 2
  • <pulse_ON_T2>, Pulse enable for Terminal 2
  • dcbrk > dc link breaker
  • <ac1_brk> ac breaker in Terminal 1 , when open there is a charging R connected, when close the charging R is bypassed.
  • <ac2_brk> ac breaker in Terminal 2 , when open there is a charging R connected, when close the charging R is bypassed.
• Load and execute the model, make sure all above variables are “0”.
• Set the MMC Parameters block.
  
  • Set the MMC SM type and SM number ( HBSM, FBSM, CDSM or mixed types)
  • Maximum number of SM types in one arm is 3 (From group 1 to group 3). Select “disabled” if corresponding SM group is not used
  • “capacitor voltage base” should be set as dc voltage divided by the total number of SM capacitors

• Set the MMC Parameters block.
  
  • Set < Vcap mode> to “normal operation”
  • For FBSM, “force bit for FBSM” should be selected during the diode conducting mode to charge the capacitors of FBSM as HBSM
  • For CDSM, “g5 (CDSM)” should be enabled
  • Check “enable pulse” to apply the gating signals

• Set the MMC Parameters block.
  
  • “gating signal from” selected as “embedded VBC in FPGA
  • Set the carrier frequency (Hz), eg 300

• Set <ac1_brk> =1 and <ac2_brk>=1 to bypass charging resistance to charge the MMC. Observe the Vcap and Vdc increase.
• In both sides, enable the pulse. Observe the Vcap and Vdc is controlled to 1 pu . Q equals its reference,
• Change Qref at both sides and observe the actual Q follows the reference. (note this time dc link breaker is open, both side MMC operates as STATCOM and Pref =0)
• Close dc link by setting < dcbrk > =1, change Pref and Qref

• Observe the Vcap and Vdc is controlled to 1 p.u. P and Q follow their references

MMC STATCOM Demo Model: Full-Bridge Topology

• The MMC system demo model is to further test the MMC model by operating it in a power system.
• An MMC STATCOM system is served for this purpose.
• In this model, the STATCOM MMC model is simulated on FPGA other than CPU.

The model can be controlled and the simulation results can be monitored during simulation in the console subsystem as below.

For the control

• ctrl mode set the STATCOM either in voltage mode or Q mode. The voltage mode controls the voltage at PCC to 1 p.u . as long as reactive power allows. The Q mode control the reactive power to the set value set at the q_ref
• load shed is to connect to (=1) or shed (=0) the load.
• ac no_fault is to set a 0.05sec (adjustable in the model) 3 phase ground fault at PCC.
• voltage sag test2 is to set voltage sag at source bus (0 for no sag, and 0.1 for 0.1 p.u. voltage sag).
• data_logging is to start or stop data logging.
• MMC para is to set the MMC parameters which is explained in the previous section.
• MMC fault is to set the different fault patterns.
• MMC pulse is to set the gate signals for each cells.

For the monitoring

• The first scope “ measscope ” displays respectively from the topmost to the lowermost sub scopes:
• 3 phase voltages at the Bus PCC.
• 3 phase currents at the Bus PCC.
• 3 phase active and reactive powers at the Bus PCC.
• 3 phase STATCOM currents.
• 4 signals, i.e. STATCOM voltages in phases a, b, c, and neutral.
• 3 signals, i.e. source bus voltages in phases a, b, and c.
• The second scope displays following signals from the topmost to the lowermost sub scopes respectively:
• 6 MMC valve voltage references from the control.
• MMC cell capacitor average voltages at each valve.
• 192 signals, i.e. the voltages of 192 capacitors, the first 96 data are 32 capacitor voltages of the selected group, the last 96 data shows the first Vcap of each group in each valve.
• 5 signals, i.e. the maximum and minimum values of the capacitor voltage and the first three capacitor voltages.
• 2 signals, i.e. the counter signals determining the voltages of which groups of capacitors will be displayed.

Real-time Performance

• The model has been run on a dual Xeon based 3.466 GHz CPU with Red hat operating system. The time step is 20 µs, and 2 CPU cores have been assigned. Note the time step is as short as 20 µs and the CPU usage for the power system simulation including the MMC STATCOM is 38.17%.

• Load and execute the model.
• In the “MMC parameter” block, set < Vcap mode> to “normal operation”, <pulse source>to “reference from CPU & pulse generated in FPGA with VBC”, <number of cell per half arm>=30, <cell capacitance> = Ccal
• In the “MMC parameter” block, check the option enable pulse .
• Switch “ctrl mode” to 1 “Volt ctrl”, switch “load shed” to 1, “ac no_fault ” to 0, switch “voltage sag” to 0. (Result 1)

• Load and execute the model.
• In the “MMC parameter” block, set < Vcap mode> to “normal operation”, <pulse source>to “reference from CPU & pulse generated in FPGA with VBC”, <number of cell per half arm>=30, <cell capacitance> = Ccal
• In the “MMC parameter” block, check the option enable pulse .
• Switch “ctrl mode” to 1 “Volt ctrl”, switch “load shed” to 1, “ac no_fault ” to 0, switch “voltage sag” to “Step 1”. (Result 2)