Software Version Requirements

• Vivado 2017.4
• Matlab 2016b (64 bit)
• RTXSG 3.1

Make Your System Generator Design

• Make sure the “System Generator” is on top level
• Setup the system generator GUI in Synthesized Checkpoint compilation mode:

Make Your Sysgen Design

• Setup the system generator GUI with your FPGA device
  
  • V707= xc7vx485t 2ffg1761
  • K7= xc7k410t 1ffg676

• Select your target directory (this is where you will find the dcp and vhd files after the generation)

• In the Clocking Tab, select your frequency (10ns/1e-8 for 100MHz or 5ns/5e-9 for 200MHz)

• Add Gateway in/out todefine your design input and output
• Rename the Gateway in/out as the names theinport/output of the blackbox you want

• Setup your gateway in with the right format and sample time

• Leave your gateway out setup as default

• Make sure there is no "Synthesis Manager" block in your model

Generate Your NGC

• Now that your design update or play correctly, press the generate button to generate your design.

Verify the Timing

• In the sysgen report, make sure the timing met respects your constraints
• If it does not, it is recommended to improve your timing result before the blackbox integration in the full design
• The information can also be found in netlist/synth_model/<design_name>.results.

Loof for the Generated Files

• In the target repository, the 2 important files are:
  • <design_name>.dcp and
  • <design_name>_stuf.vhd

Understand the Generated Files

• In this case:
  • DCP: contains the logic
  • VHD: contains the input-output mapping
• Open the VHD file, add this line to the part of entity and save the file

Copy the Generated Files

• Copy the <design_name>.dcp and <design_name>_stub.vhd filesto your top level design folder

Open the Top Level Design

• Verify the right board is selected at the right frequency in the Synthesis Manager block

Add the Blackbox in the Top Level Design

• Create a new Simulink model and save it, drag a Blackbox bloc from the library to the model

• Open the <design_name>_stub.vhd in the GUI

Edit the _config.m File

• After selecting the vhd file, a *_config.m file will open in the Matlab editor
• This file is used to do the interface with Simulink and contains information such as:
  
  • Port mapping
  • Combinational design
  • Output type
  • Input bit vectors checking
  • Source VHD file
  • Rate properties
  • Etc…
• If your design is not purely combinational, comment the line "this_block.tagAsCombination;"

• Reshuffle the inport/outport order as you want

• Select the outport type according to the blackbox source design if necessary

• Later in the file, modify the line
  • this_blcok.addFile(<vhdfilename>_stub.vhd) with this_block.addFile(which(<vhdfilename>_stub.vhd))

• Save the modification

Connect the Blackbox to Your Model

• Add Assert block on the black box inputs
• Assert the type and rate according to the gateway in of the black box source design

• For all inport

• Connect the black box in_out to your top level design
• Update the model and verify the model can update and signals' types are correct

Generate the Bitstream

• Verify one last time the board and frequency
• DCP and VHD file must be in the model folder
• Define the name, version ID and minor ID of the bitstream, the generate the bitstream

• Verify the ngc file has been transferred properly in the Matlab command prompt window

• Wait for your bitstream to compile