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Location

This example model can be found in the MMC installation folder under the directory of /Examples/MMC_HVDC_P2P/

Introduction

This demo simulates the an HVDC link with two MMC stations. Each MMC model can be implemented in CPU or in FPGA. In the CPU implementation, the MMC can be modeled in detailed Switching Function (SWF) and Average (AVM) Models, while in FPGA implementation, only a detailed SWF model is available.

The selection of CPU and FPGA is defined in the initialization file (init_HVDC_2Stations_MMC.m) included in the same folder of the Simulink file. Based the type of study, the users can choose CPU or FPGA model type. Users should change the model type from one to another before running the simulation by uncommenting the appropriate model selection for each MMC in the initialization file.

The MMCs in this demo are modeled using the provided RT-Lab MMC Valves block, which can be used for half-bridge, full-bridge, and clamp double MMC submodules (SMs) for both CPU and FPGA modes of operation. Please also take a look at the full bridge MMC STATCOM demo. The demo shows that the CPU model can be simulated either in offline mode with a much faster simulation speed than other offline simulation software or in real-time.

This demo demonstrates the MMC using HB Sub-Module (HBSM), but the model can be also configured to model different SM types, including half-bridge, full-bridge, clamp-double, and T-type MMC cells. In the actual demo the control is adapted only for HBSM and FBSM implementations.

The MMC block models up to a maximum of 50 individual MMC SMs per valve in the CPU implementation. Multiple MMC blocks can be piled up to model an MMC valve of more than 50 SMs, however this will limit the performance in real time and thus for models with more than 50 SMs per valve it is recommended to use the FPGA implementation. In the FPGA mode of operation, the number of SMs is limited by the user license. In the standard firmware, the FPGA model supports up to 511 SMs per valve, more can be added upon request.

Moreover, the MMC block has the following features. More details and features are presented in the overview of the MMC Valves library.

• The values of cell capacitance and the discharge resistance can be adjusted during simulation.

• There is a dead time between each pair of upper and lower gates.

• Temporary or permanent short circuits of SM capacitors in any SM can be simulated.

• There are normal and debugging modes. In the debugging mode, the capacitor voltages can be set to an average value (to replace voltage balance control temporarily) or a fixed value.

The demo is structured in three main sub-systems:

• SC_Console: Is the console subsystem. Contains the displays, constant blocks and parameter blocks to interact with the model when it is running. In the console the power references can be set and the simulation waveforms are displayed in scopes. The console includes also the MMC Valves parameter blocks to set some of the parameters to the MMCs in the simulation.

• SM_MMC1etCntrl: Contains the high level control for both MMC stations and the model of the first MMC station. In the MMC station model the different electrical elements (transformer, breakers, AC grid) are included and also the MMC Valves block that implements the model of the MMC. The low level control of this station is also included in the corresponding MMC Valves Low Level block.

• SS_MMC2: Contains the model of the second MMC station. This includes the different electrical elements (transformer, breakers, AC grid), the MMC Valves block that implements the model of the MMC, and the low level control of this station in the MMC Valves Low Level block.

Circuit Description

The MMC HVDC demo is studied in a test system as in Figures 1 and 2 shown below. The corresponding parameters are given in Table 1.

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Figure 1. Overall point-to-point MMC HVDC system

Demonstration and Simulation

Various phenomena can be studied using this MMC HVDC model. For example, with this demo model, the steady state, transients and faults can be studied. The model can be controlled and the simulation results can be monitored during simulation in the console subsystem, as shown in below figure 5.

For the control:

The value of Pac can be adjusted between -0.8 to 0.8 p.u., whereas QacT1 and QacT2 can be adjusted between -0.3 p.u. to 0.3 p.u. By changing these values, the active and reactive power can be controlled to the desired level.

To enable the control on each MMC station, the Enable Pulses option on each MMC Valves parameter block (for terminal 1 and 2), should be enabled.

The DataLog option can be set to either 1 (the data logging is enabled) or 0 (the data logging is disabled). This option enable user to store the scope data in a MATLAB file directly from the real time simulation. The file can be seen inside the user workspace and then the data can be analyzed offline post simulation.

The status of all of the DCCB, ACCBT1 and ACCBT2 can be set to either 1 or 0, when the breaker is set to 1, it is closed and otherwise it is opened, when it is opened, the circuit is broken from dc or ac at left or right terminal respectively.

For the monitoring:

The two scopes "T1 and T2" display the following measurements of terminal 1 and terminal 2. In the below signals all measurements are in p.u. except MMC valve voltages which are in SI units.

1. DC voltage.

2. DC current.

3. 3-phase voltages.

4. 3-phase currents.

5. 3-phase active and reactive powers.

6. MMC arm current.

7. MMC valve voltages.

8. MMC SM capacitor valve average voltages.

Operating procedure:

1. When the system starts pre-charge, at that time all of the breakers (include dc and ac breakers) are opened, both of the pulses are off, the capacitors are pre-charged, and the dc voltage for the left terminal should be charged to around 0.6 pu.

2. After pre-charging of the capacitors finished, close the left terminal ac breaker, both of the pulses are off, the dc voltage for the left terminal is charged to around 0.7 pu.

3. Enable the pulse of the left terminal, the dc voltage for the left terminal is 1 p.u.

4. Set the reference value of the reactive power of the left terminal, the real Q value should be the same as the reference Q value.

5. All the above steps are the same for the right terminal.

6. After finishing the above steps for both left and right terminals, close the dc breaker and see the dc voltages on both sides, set the reference value of the real power P, the real value of P should track the reference value.

Notes for FPGA implementation:

For real-time simulation in FPGA type of model ensure the appropriate Board ID and bitstream file have been chosen. The user can set these details for MMC1 inside the subsystem “SM_MMC1_and_Ctrl/MMCStation1/MMCModel/Model/MMCinFPGA”.

For MMC2 in the subsystem “SS_MMC2/MMCStation2/MMCModel/Model/MMCinFPGA_wOpLnk” if MMC1 is set as FPGA model type or else in “SS_MMC2/MMCStation2/MMCModel/Model/MMCinFPGA_wOpCtrl“.

Inside these subsystems, the user can find the OpCtrl (or OpLnk) block where the Board ID and bitstream filenames must be set as shown in below figure 6.

Further, in RT-LAB under the Execution tab, the Real-Time simulation mode has to be set before building the model. If the model type is CPU for both MMCs the user must use “Software Synchronization”, whereas in FPGA type model is chosen for any one of MMC or both this need to be changed to “Hardware synchronized”, as shown in Figure. 7.

Results

The results demonstrate two test cases. The Case1 used to demonstrate the CPU model type and Case2 used to demonstrate the FPGA model type along with results showing the operating procedure and corresponding response from terminal 1 and terminal 2.

Case1: In this case, the terminal 1 and terminal 2 are in CPU model type. More precisely, terminal 1 and 2 models are chosen as SFM and AVM respectively. It follows the same operating procedure as discussed above from points 1 to 6. The below figures 8 and 9 are terminal 1 and terminal 2 measurements as explained above. The set-points are chosen as Pac=0.8 p.u., and QacT1 and QacT2 as 0 p.u.

Case 2: In this case, the terminal 1 and terminal 2 are operating in FPGA model type. The same operating procedure as discussed above from points 1 to 9 are followed. The below figures 10 and 11 are terminal 1 and terminal 2 measurements as explained above. The set-points chosen as Pac is 0.8 p.u., QacT1 and QacT2 as -0.3 p.u and 0.2 pu, respectively.

It follows the step-by step results for both MMC stations s start-up sequence, the responses are shown in figure 10 and 11 for terminal 1 and terminal 2, respectively. Further, figures are illustrated below:

• Simulation starts at t=0 s, all the breakers are open, pulses are disabled, and set-points are set to zero.

• ACCBT1 is closed around t=0.225 s and pulse for MMC1 is enabled at t=0.35 s.

• ACCBT2 is closed around t=0.56 s and pulse for MMC1 is enabled at t=0.77 s.

• DCCB is closed around at t=1.05 s.

• The response during these CBs closing and pulses enable for both MMC1 and MMC2 can observe in terminal 1 and terminal 2.

• At t=1.33, active power reference Pac is set as 0.8 p.u., Around t= 0.2s and t=0.26 s, QacT1 and QacT2 set-points changed are set as -0.3 p.u. and 0.2 p.u., respectively.

References

1. W. Li et J. Belanger, “An equivalent circuit method for modelling and simulation of modular multilevel converters in real-time HIL test bench,” IEEE Transactions on Power Delivery, vol. 31, no. 15, pp. 240—2409, 2016.

2. W. Li, L. -A. Grégoire and J. Bélanger, "A Modular Multilevel Converter Pulse Generation and Capacitor Voltage Balance Method Optimized for FPGA Implementation," in IEEE Transactions on Industrial Electronics, vol. 62, no. 5, pp. 2859-2867, May 2015, doi: 10.1109/TIE.2014.2362879.