Page Content

1 Location
2 Introduction
3 Circuit Description
4 Demonstration and Simulation
5 Results
6 References

Location

This example model can be found in the MMC installation folder under the directory of /Examples/MMC_Matrix_Converter/

Introduction

This demo simulates a Modular Multilevel Matrix Converter (M3C) station. The M3C model can be implemented in CPU or in FPGA. In the CPU implementation, the MMC can be modeled in detailed Switching Function (SWF) and Average (AVM) Models, while in FPGA implementation, only a detailed SWF model is available.

The selection of CPU and FPGA is defined in the initialization file (parameters_M3C.m) included in the same folder of the Simulink file. Based on the type of study, the users can choose CPU or FPGA model type. Users should change the model type from one to another before running the simulation by uncommenting the appropriate model selection for M3C in the initialization file.

The converter in this demo are modeled using the provided RT-Lab MMC Valves block, which can be used for half-bridge, full-bridge, and clamp double MMC submodules (SMs) for both CPU and FPGA modes of operation. This demo demonstrates the MMC using FB Sub-Module (FBSMs).

The MMC block models up to a maximum of 50 individual MMC SMs per valve in the CPU implementation. Multiple MMC blocks can be piled up to model an MMC valve of more than 50 SMs, however this will limit the performance in real time and thus for models with more than 50 SMs per valve it is recommended to use the FPGA implementation. In the FPGA mode of operation, the number of SMs is limited by the user license. In the standard firmware, the FPGA model supports up to 511 SMs per valve, more can be added upon request.

Moreover, the MMC block has the following features. More details and features are presented in the overview of the MMC Valves library.

The values of cell capacitance and the discharge resistance can be adjusted during simulation.
There is a dead time between each pair of upper and lower gates.
Temporary or permanent short circuits of SM capacitors in any SM can be simulated.
There are normal and debugging modes. In the debugging mode, the capacitor voltages can be set to an average value (to replace voltage balance control temporarily) or a fixed value.

The demo is structured in three main sub-systems:

SC_Console: is the console subsystem. Contains the displays, constant blocks, and parameter blocks to interact with the model when it is running. In the console, the power references can be set and the simulation waveforms are displayed in scopes. The console includes also the MMC Valves parameter blocks to set some of the parameters to the MMCs in the simulation.
SM_M3CControl: Contains the high-level control for the M3C model.
SS_M3CPlant: Contains the model of the M3C station. This includes the different electrical elements (three-phase RLC branches, AC grids), the MMC Valves block that implements the model of the M3C, and the low-level control of this M3C station is implemented with the MMC Valves Low Level block.

Circuit Description

This M3C demo shows the application of 10 MVA interconnection of two AC grids with frequencies F1 & F2 (F1≠ F2, & F1 and/or F2 ≠ 0). Figure 1 shows the schematic of the system. In this example, the M3C is intended for achieving ac-to-ac bidirectional power exchange between the two AC grids. The higher-level control design, system parameters, and control parameters evaluation are discussed on this sub-page of the M3C model.

Figure 1 Schematic representation of M3C interconnecting two AC-grids with different frequencies.

Demonstration and Simulation

The power flow between the grids can be controlled during the simulation by varying the power references Pref, Q1ref, & Q2ref provided in the console as shown in the below figure. It should be noted that the effective apparent power of the references should not cross the nominal power of the converter.

For the control:

Pref	set point of the active power reference in p.u.
Q1ref	set point of the reactive power reference at M3C input in p.u.
Q2ref	set point of the reactive power reference at M3C output in p.u.
MMC parameters	set the MMC parameters based on model type, details can be found in MMC Valves parameter. In the demo the values on the mask have been set accordingly to the initialization file variables.
Enable Pulses (inside the MMC parameter blocks mask)	Enable or disable the gating signals (pulses). This is done inside the MMC parameter blocks mask.

The value of Pref can be adjusted between -1 to 1 p.u., whereas Q1ref and Q2ref can be adjusted between -1 p.u. to 1 p.u. By changing these values, the active and reactive power can be controlled to the desired level. However, one needs to pay attention the effective apparent power should not cross the nominal power, i.e., in this case 10 MW.

To enable the control on each M3C station, the Enable Pulses option on MMC Valves parameter block (for M3C), should be enabled.

For the monitoring:

The two scopes say, scope1 and scope2 display the following measurements. In the below signals, all measurements are in p.u. except MMC valve voltages which are in per units.

3-phase voltages inputs.
3-phase currents inputs.
3-phase voltages outputs.
3-phase currents outputs.
3-phase active powers set-points and output.
3-phase reactive powers set-points.
3-phase reactive powers outputs.
MMC SM capacitor valve average voltages.
Inputs 1 and 3 are per-unit valve voltages and inputs 2 nad 4 are per unit currents (see Scope2)

Notes for FPGA implementation:

For real-time simulation in FPGA type of model ensure the appropriate Board ID and bitstream file have been chosen. The user can set these details for MMC inside the subsystem “Lib_M3C_Demo/SS_M3CPlant/MMCModel/Model/MMCinFPGA”. Inside these subsystems, the user can find the OpCtrl (or OpLnk) block where the Board ID and bitstream filenames must be set as shown in below figure.

Further, in RT-LAB under the Execution tab, the Real-Time simulation mode has to be set before building the model. If the model type is CPU the user must use “Software Synchronization”, whereas in FPGA type model, this need to be changed to “Hardware synchronized”, as shown in the below figure.

Results

The control of the M3C converter is demonstrated with the offline & real-time simulation results. The test scenarios defined for the validation of the control in both offline & real-time are as follows:

Offline Results:

Test Scenario – 01: Transfer of active power from input to output. The control of M3C is enabled at 0.25 seconds & the DC-link voltage is regulated to its reference. A step change in active power reference from 0 to nominal (1 P.U) is applied at 5 s. Figure 1 to 4 illustrates the input & output voltages, currents, active-reactive powers & DC-link voltage for steady-state & dynamic response of the control. Further, Figure 5 to 7 illustrates the valve voltages, currents in abc-frame & double-αβ frame, & valve capacitor voltages in double- αβ frame which demonstrates the functionality of double- αβ frame control for M3C.

Test Scenario – 02: Transfer of active & reactive power at 0.6 P.F. Similar to the scenario-01, the control of M3C is enabled at 0.25 seconds & the DC-link voltage is regulated to its reference. A step change in active power reference 0.8 P.U is applied from starting and a step change in reactive power from 0 to 0.6 P.U is applied at 5 seconds. Figure 8 and 9 illustrate the input & output voltages, currents, active-reactive powers & DC-link voltage for steady-state & dynamic conditions.

Real-time Results:

Similar to the offline test scenario’s, the real-time model is tested, and the sample results are presented in Figure 11, & 12. The active power reference is set to 0.8 P.U and the output reactive power reference is to 0.6 P.U. The results illustrate the proper working of converter control. The real time CPU model of this example is implemented in two cores by segregating it the into master and one-slave subsystem. The master subsystem consists of top-level control and the slave consists of plant (M3C interconnecting two AC grids). The step-time for the implementation the real-time model is Ts = 30μs. The online CPU computational burden [SM ≈ 6%, & SS ≈ 67% ] is shown in Figure 10, where the model is running without any overruns.

The RT-Lab Demo on the application of a M3C is developed and presented in this report. In this demo, the M3C converter interfaces the two-ac grids with frequencies F1 & F2 (F1≠ F2, & F1 and/or F2 ≠ 0). The control for M3C is developed based on the double-αβ reference frame. The objectives of the control are active & reactive power exchange/transfer, input & output current regulation, DC-link capacitor voltage regulation, circulating current control for balancing of valve capacitor voltages and independent sub-module capacitor voltage balancing. All the control objectives are well achieved. The detailed design of the converter parameters and controller gains are presented in this sub-page.

References

W. Li et J. Belanger, “An equivalent circuit method for modelling and simulation of modular multilevel converters in real-time HIL test bench,” IEEE Transactions on Power Delivery, vol. 31, no. 15, pp. 240—2409, 2016.
W. Li, L. -A. Grégoire and J. Bélanger, "A Modular Multilevel Converter Pulse Generation and Capacitor Voltage Balance Method Optimized for FPGA Implementation," in IEEE Transactions on Industrial Electronics, vol. 62, no. 5, pp. 2859-2867, May 2015, doi: 10.1109/TIE.2014.2362879.