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Location

This example model can be found in the MMC installation folder under the directory of /Examples/MMC_HVDC_Bipole/

Introduction

This demo simulates a Bipolar HVDC link. Each MMC model can be implemented in CPU or in FPGA.

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Figure 1. HVDC Bipole example

The selection of CPU and FPGA is defined in the “DEMOModelConfig” block inside the console sub-system. Users should change the model type from one to another before running the simulation by selecting the appropriate option in the block.

The MMCs in this demo are modeled using the provided RT-Lab MMC library. It can be simulated in real time or in offline mode. The CPU implementation supports average and switched function model, while the FPGA implementation only switched function model. Refer to the MMC library for details.

In this this demo, the MMCs use Half Bridge Sub-Modules (HBSM), but the model can be also configured for other SM types, including full-bridge, clamp-double, and T-type SMs. In the actual demo example the provided control is adapted for HBSM and FBSM implementations.

The demo is structured in three main sub-systems:

• SC_Console: Is the console subsystem. Contains the data scopes, the “DEMOModelConfig” block and a “MMC_Bipole Console” block to set the references to the controller, operate the breakers and the converters. Inside this last block the user will find the MMC Valves parameter blocks that set parameters for each MMC.

• SM_Control1: Contains the high level control for both stations taking into account the control of each individual MMC on each station (positive and negative pole MMC).

• SS_MMC1: Contains the model of the first converter station. This includes the different electrical elements (transformer, breakers, AC grid) and also the MMC Valves block that implements the model of the MMCs. Two MMCs are modeled, one connected to the positive pole and one to the negative pole. The low level control of this station is also included in the corresponding MMC Valves Low Level block.

• SS_MMC2: Contains the model of the second converter station. It is similar to SS_MMC1.

Circuit Description

The test system of this demo is presented in Figure 1. The corresponding parameters are given in Table 1.

Demonstration and Simulation

Various phenomena can be studied using this Bipole HVDC model. For example, with this demo model, the steady state, transients and faults can be studied. The model can be controlled and the simulation results can be monitored during simulation in the console subsystem or saved in a file using the OpWriteFile block to study the RT data without loss of information. As shown below in Figure 2, the simulation results can be observed in the displays and the block “MMC_Bipole Console” allows to set the references to the system.

Further, it is suggested to the users that don’t change the name or position in the sub-system hierarchy of the MMC Valves library blocks used in the demo model if the user is using the DemoModelConfig block.

For the control:

The user can use the different options on the “MMC_Bipole Console” block. Note that this is a masked sub-system, inside the user can find the MMC Valves parameter blocks for the 4 MMCs in the example.

The value of Pac can be adjusted between -0.8 to 0.8 p.u., whereas QacT1 and QacT2 can be adjusted between -0.3 p.u. to 0.3 p.u. By changing these values, the active and reactive power can be controlled to the desired level.

To enable the control on each MMC station, the Enable Pulses should be activated.

For the monitoring:

There are three scopes in the console. The scope "VImmc_T12" and “VImmc_T34” display the following measurements of MMC1 and MMC2, and MMC3 and MMC4 respectively (all measurements are in p.u.)

1. DC current on positive and negative terminals. The positive convention is coming from the MMC and going into the DC line.

2. DC voltage between both terminals on each MMC. This is equivalent to the pole-to-ground voltage in the bipole.

3. MMC valve voltage. The voltage measured at the terminals of each converter valve.

4. MMC arm current. The current on each valve; being the positive convention entering into the positive terminal of the valve.

5. MMC equivalent capacitor voltage. This is the average value of all the valve SM capacitor voltages.

6. Reference voltages. This is the voltage reference for each MMC valve coming from the high level control stage.

The scope "VIac_T1234" displays the following measurements for the four MMCs (all measurements are in p.u.) :

1. AC voltages at the MMC terminals. The voltage is measured as phase to ground.

2. AC currents on each MMC. The convention is positive going out from the MMC and entering into the AC system.

3. AC active and reactive powers on the MMC terminals.

4. The DC voltage at the MMC terminals

Operating procedure:

1. When the system starts pre-charge, at that time all of the breakers (include dc and ac breakers) are opened, the converter pulses are off. The capacitors and the DC side are pre-charged at around 0.6 p.u.

2. After the pre-charge is finished, close the AC breakers keeping the pulses disabled. The dc voltage should increase to around 0.7 p.u.

3. Close the DC breakers and enable the pulses keeping the power references at zero. The dc voltage and the capacitor voltages should be controlled to 1 p.u.

4. Set the reference value of the reactive and active powers and see how the reference are tracked.

5. All the above steps are the same for the right terminal.

6. After finishing the above steps for both left and right terminals, close the dc breaker and see the dc voltages on both sides, set the reference value of the real power P, the real value of P should track the reference value.

Notes for FPGA implementation:

For real-time simulation in FPGA, the OpCntrl and OpLink blocks placed in MMC_Bipole1/SS_MMC1 and MMC_Bipole1/SS_MMC2 respectively should uncommented. This is done automatically by using the provided “DEMOModelConfig” block in the console. However the user must ensure the appropriate Board ID and bitstream file configuration on those blocks. Inside these subsystems, the user can find the OpCtrl (or OpLnk) block where the Board ID and bitstream filenames must be set as shown in below figure 6.

Further, in RT-LAB under the Execution tab, the Real-Time simulation mode has to be set before building the model. If the model type is CPU for all MMCs the user must use “Software Synchronization”, whereas in FPGA type model is chosen for any one of the MMCs this need to be changed to “Hardware synchronized”, as shown in Figure. 7.

References

1. W. Li et J. Belanger, “An equivalent circuit method for modelling and simulation of modular multilevel converters in real-time HIL test bench,” IEEE Transactions on Power Delivery, vol. 31, no. 15, pp. 240—2409, 2016.

2. W. Li, L. -A. Grégoire and J. Bélanger, "A Modular Multilevel Converter Pulse Generation and Capacitor Voltage Balance Method Optimized for FPGA Implementation," in IEEE Transactions on Industrial Electronics, vol. 62, no. 5, pp. 2859-2867, May 2015, doi: 10.1109/TIE.2014.2362879.