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Location

This example model can be found in the MMC installation folder under the directory of /Examples/MMC_MTDC/

Introduction

This demo simulates a Multi-Terminal HVDC (MTDC) grid with four MMC stations. Each MMC model can be implemented in CPU or in FPGA. In the CPU implementation, the MMC can be modeled in detailed Switching Function (SWF) or Average (AVM) Models, while in FPGA implementation, only a detailed SWF model is available (see Overview of the MMC Valves Library and MMCValves Block for more information of the type of models). The DEMO parameters are initialized using the initialization file (init_MMC_MTDC.m) provided with the example.

The selection of CPU or FPGA implementation is set using the DemoModelConfig block (placed in the SC_console suybsystem), as shown in Figure 1. Based on the type of study, the users can choose CPU or FPGA model type. Users should change the model type from one to another before running/ compiling the simulation by selecting the appropriate model selection for each MMC station as shown below. This block gives the user an easy way to change the model type for each MMC station. Alternatively, the user can also change the model type manually without using this block; in this case, the user needs to be a bit careful to change the model type appropriately for all associated blocks that require model type, say MMCValves Block, and for each MMC station.

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Figure 1: Demo Model Configure

The MMCs in this demo are modeled using the provided RT-Lab MMC Valves block, which can be used for half-bridge, full-bridge, and clamp double MMC submodules (SMs) for both CPU and FPGA modes of operation. Please also take a look at other MMC demo models. These demos show that the CPU model can be simulated either in offline mode with a much faster simulation speed than other offline simulation software or in real-time. This demo demonstrates the MMC using Half-Bridge HB Sub-Module (HBSM) but the model be configured to model other SM types, say FBSM and CDSM. However, in the actual demo, the control is adapted only for HBSM and FBSM implementations.

Each MMC block models up to a maximum of 50 individual MMC SMs per valve in the CPU SWF implementation. Multiple MMC blocks can be piled up to model an MMC valve of more than 50 SMs. However, this will limit the real-time performance; thus, for models with more than 50 SMs per valve, it is recommended to use the FPGA implementation. In the FPGA mode of operation, the number of SMs is limited by the user license. In the standard firmware, the FPGA model supports up to 511 SMs per valve; more can be added upon request. For CPU AVM implementation there is no limit in the number of SMs.

Moreover, the MMC block has the following features. More details and features are presented in the overview of the MMC Valves library.

• The values of cell capacitance and the discharge resistance can be adjusted during simulation.

• There is a dead time between each pair of upper and lower gates.

• Temporary or permanent short circuits of SM capacitors in any SM can be simulated.

• There are normal and debugging modes. In the debugging mode, the capacitor voltages can be set to an average value (to replace voltage balance control temporarily) or a fixed value.

The demo is structured majorly in three main sub-systems:

• SC_Console: is the console subsystem. It contains the displays, the DemoModelConfig block, and the MTDC grid reference control block which consists of constant blocks to set the control references on the model and the MMC Valves parameter blocks to configure each MMC. The SC_Console allows to interact with the model when it is running. The power references can be set using this control block (MTDC Grid Console), and the corresponding simulation waveforms are displayed in scopes.

• SM_Control: Contains the high-level control for all four MMC stations.

• SS_MMC1, SS_MMC2,SS_MMC3, and SS_MMC4: Are the subsystems containing the MMC station models, the different electrical elements (transformer, breakers, AC grid) are included, as well as the MMC Valves block that implements the model of the MMC. The low-level control of the station is also included in the corresponding MMC Valves Low Level block.

Circuit Description

This example shows how to simulate a four terminal DC grid power system with four MMC converters. The number of SMs per arms is moderate in this demo (=50). For cases with much higher number of SMs, up to 512 per arm, it is recommended to model the MMC on FPGA.

 The model has a similar grid configuration as Benchmark Model, say BM1 in CIGRE B4-72. The dc voltage is controlled by Terminal2 (MMC_T2 as shown in below figure). The other terminals are operating in constant PQ control. See [1] for further details. The MMC HVDC demo is studied in a test system as in Figures 2 and 3 shown below. The corresponding parameters are given in Table 1.

Demonstration and Simulation

Various phenomena can be studied using this MMC MTDC model. For example, with this demo model, the steady state, transients and faults can be studied. The model can be controlled and the simulation results can be monitored during simulation in the console subsystem, as shown in below figure 4. Further, it is suggested to the users that don’t change the blocks name in the demo model or in console if the user is using the DemoModelConfig block.

For the control:

The value of active power can be adjusted between -1 p.u. to 1 p.u., whereas Q1, Q2, Q3 and Q4 can be adjusted between -0.3 p.u. to 0.3 p.u. Changing these values allows active and reactive power to be controlled to the desired level.

The DataLog option can be seen inside the MTDC Grid Control Block and set to either 1 (the data logging is enabled) or 0 (the data logging is disabled). This option enables user to store the scope data in a MATLAB file directly from the real time simulation. The file can be seen inside the user workspace and then the data can be analyzed offline post simulation. By enabling data logging and data logging1 the scope data of Terminals 1,2 (of scope1 in MMC_MTDC/SM_Control/SM_ControlT12) and Terminals 3,4 (of scope3 in MMC_MTDC/SM_Control/SS_ControlT34) data is stored in .mat file (one can fetch these mat files in opal-rt workspace, say, Project_name\models\MMC_MTDC\mmc_mtdc_sm_control\OpREDHAWKtarget.

The status of all the DC breakers and AC breakers can be set to either 1 or 0, when the breaker is set to 1, it is closed and otherwise it is opened, when it is opened, the circuit is broken from dc or ac at left or right terminal respectively.

For the monitoring:

The three scopes "VImmcT12, VIac_T1234 and VLmmcT34" display the following measurements of all four terminals. In the below signals all measurements are in p.u.

1. DC current.

2. DC voltage.

3. MMC arm voltages.

4. MMC valve currents.

5. MMC SM capacitor valve average voltages.

6. Voltage reference from Higher level control.

Whereas VIacT1234 shows the AC signals of all four terminals such as

1. 3-phase voltages.

2. 3-phase currents.

3. 3-phase active and reactive powers.

Operating procedure:

1. When the system starts pre-charge, at that time all of the breakers (include dc and ac breakers) are opened, both of the pulses are off, the capacitors are pre-charged, and the dc voltage for all the terminals should be charged to around 0.6 p.u.

2. After pre-charging of the capacitors finished, close the ac breakers, the dc voltage for all the terminal is charged to around 0.7 p.u.

3. Enable the pulse of all the terminal, the dc voltage for all the terminals will be around 1 p.u.

4. After finishing the above steps, close the dc breakers and see the dc voltages on each terminal.

5. Set the reference value of the active and reactive power of all the terminals and track these reference values.

Notes for FPGA implementation:

For real-time simulation in FPGA type of model ensure the appropriate Board ID and bitstream file have been chosen. The user can set these details for MMCs inside the subsystem, let say for MMC1 the user can found it here “MMC_MTDC/SS_MMC1/MMCModel/MMC” and similarly these details can see for the other MMC stations.

Inside these subsystems, the user can find the OpCtrl (or OpLnk) block where the Board ID and bitstream filenames must be set as shown in figure 5 below. Moreover, the DemoModelConfig block in the console ensures the appropriate OpCtrl (or OpLnk) is uncommented on each MMC station based on the selection of FPGA model type for stations by the user. However, the user needs to bring his attention while commenting and uncommenting OpCtrl (or OpLnk) while changing the model type manually without using the DemoModelConfig block .

Further, in RT-LAB under the Execution tab, the Real-Time simulation mode must be set before running the model. If the model type is CPU for all MMCs the user must use “Software Synchronization”, whereas in FPGA type model is chosen for any one of MMC stations this need to be changed to “Hardware synchronized”, as shown in Figure. 6.

Simulation Results

The results demonstrate the transients and steady-state dynamics of MTDC grid during active power and reactive power set-points changes. Further, it also shows the starting procedure of the MTDC grid. In this scenario all terminals are operating in CPU-AVM model type at simulation time step (Ts) of 35 usec.

After following the above discussed operating procedure by closing AC breakers at t=0.2 sec, enabling pulses at t=0.41 sec, ensured the DC voltages in DC grid reached to 0.7 p.u., and then after closing DC circuit breakers after the DC voltage in DC grid is reached to 1 p.u. at t=1 sec. At t=1.5 sec, set active and reactive references are applied by using MTDC grid console, i.e., P1=0.6, P2(slack), P3=-0.4, and P4=-0.3, and Q at all the terminals are zero, whose references are also followed by the model as shown in below figures 7, 9, and 11, and respective zoomed in wave forms are shown in figures 8, 10, and 12.

Further, a change in set-points has been applied at t=2.5 secs, i.e., P1=-0.8, P2(slack), P3=0.7, and P4=0.5 and for reactive power Q1=Q3=-0.2 and Q2=Q4=0.2, respectively. The response of these change in set-points also seen in Figure 7, 8, and 9.

References

1. C. Dufour, W. Li, X. Xiao, J.-N. Paquin, J. Belanger, "Fault studies of MMC-HVDC links using FPGA and CPU on a real-time simulator with iteration capability", 11th International Conference on Compatibility, Power Electronics and Power Engineering (IEEE CPE-POWERENG 2017), Cadiz, Spain, April 4-6, 2017.

2. W. Li et J. Belanger, “An equivalent circuit method for modelling and simulation of modular multilevel converters in real-time HIL test bench,” IEEE Transactions on Power Delivery, vol. 31, no. 15, pp. 240—2409, 2016.

3. W. Li, L. -A. Grégoire and J. Bélanger, "A Modular Multilevel Converter Pulse Generation and Capacitor Voltage Balance Method Optimized for FPGA Implementation," in IEEE Transactions on Industrial Electronics, vol. 62, no. 5, pp. 2859-2867, May 2015, doi: 10.1109/TIE.2014.2362879.