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How to Make a Block Box from a System Generator Design in Vivado

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How to Make a Block Box from a System Generator Design in Vivado

Software Version Requirements

  • Vivado 2017.4
  • Matlab 2016b (64 bit)
  • RTXSG 3.1

Make Your System Generator Design

  • Make sure the “System Generator” is on top level
  • Setup the system generator GUI in Synthesized Checkpoint compilation mode:

Make your System Generator Design

Make Your Sysgen Design

  • Setup the system generator GUI with your FPGA device
    • V707= xc7vx485t 2ffg1761
    • K7= xc7k410t 1ffg676

Make your Sysgen Design

  • Select your target directory (this is where you will find the dcp and vhd files after the generation)

Target Directory

  • In the Clocking Tab, select your frequency (10ns/1e-8 for 100MHz or 5ns/5e-9 for 200MHz)

  • Add Gateway in/out todefine your design input and output
  • Rename the Gateway in/out as the names theinport/output of the blackbox you want

Make your sysgen design

  • Setup your gateway in with the right format and sample time

  • Leave your gateway out setup as default



Note: if you uncheck "translate into output port", the output will be ignored during HDL generation. It can be useful to remove debug scope signal from hdl generation.



  • Make sure there is no "Synthesis Manager" block in your model

Generate Your NGC

  • Now that your design update or play correctly, press the generate button to generate your design.

Generate your NGC

Verify the Timing

  • In the sysgen report, make sure the timing met respects your constraints
  • If it does not, it is recommended to improve your timing result before the blackbox integration in the full design
  • The information can also be found in netlist/synth_model/<design_name>.results.

Verify the Timing

Loof for the Generated Files

  • In the target repository, the 2 important files are:
    • <design_name>.dcp and
    • <design_name>_stuf.vhd

Generated Files

Understand the Generated Files

  • In this case:
    • DCP: contains the logic
    • VHD: contains the input-output mapping
  • Open the VHD file, add this line to the part of entity and save the file

Copy the Generated Files

  • Copy the <design_name>.dcp and <design_name>_stub.vhd filesto your top level design folder

Copy the generated files

Open the Top Level Design

  • Verify the right board is selected at the right frequency in the Synthesis Manager block

Synthesis Manager

Add the Blackbox in the Top Level Design

  • Create a new Simulink model and save it, drag a Blackbox bloc from the library to the model

Simulink Library Browser

  • Open the <design_name>_stub.vhd in the GUI

Edit the _config.m File

  • After selecting the vhd file, a *_config.m file will open in the Matlab editor
  • This file is used to do the interface with Simulink and contains information such as:
    • Port mapping
    • Combinational design
    • Output type
    • Input bit vectors checking
    • Source VHD file
    • Rate properties
    • Etc…
  • If your design is not purely combinational, comment the line "this_block.tagAsCombination;"



Help: Combinational: at least one input of the design affects at least one output of the design without any sampling delay.

My example design is not.

A design {A or B=C} with A and V as input and C as output is combinational, because there is no delay between C and A or between B and C.


  • Reshuffle the inport/outport order as you want

Edit the _config.m file

  • Select the outport type according to the blackbox source design if necessary

Outport Type

  • Later in the file, modify the line
    • this_blcok.addFile(<vhdfilename>_stub.vhd) with this_block.addFile(which(<vhdfilename>_stub.vhd))

Line Modification

  • Save the modification

Save the modification

Connect the Blackbox to Your Model

  • Add Assert block on the black box inputs
  • Assert the type and rate according to the gateway in of the black box source design

Connecting the Black Box

  • For all inport

Adding the Assert Block

  • Connect the black box in_out to your top level design
  • Update the model and verify the model can update and signals' types are correct

Generate the Bitstream

  • Verify one last time the board and frequency
  • DCP and VHD file must be in the model folder
  • Define the name, version ID and minor ID of the bitstream, the generate the bitstream

Generate the Bitstream

  • Verify the ngc file has been transferred properly in the Matlab command prompt window

Generating the Bitstream

  • Wait for your bitstream to compile

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