List of Abbreviations and Acronyms

• CPU Central Processing Unit
• FPGA Field Programmable Gate Array
• HIL Hardware in the Loop
• HVAC High Voltage Alternating Current
• HVDC High Voltage Direct Current
• MMC Modular Multilevel Converter
• PWM Pulse Width Modulation
• RCP Rapid Control Prototyping
• SM Submodule
  
  • CDSM Clamped Double Submodule
  • FBSM Full Bridge Submodule
  • HBSM Half-Bridge Submodule
  • T SM T type Submodule
• STATCOM Static Synchronous Compensator
• VBC Voltage Balancing Control

Nomenclature

• Ts Time step in CPU model
• Tfpga Time step (Calculation cycle) in FPGA model
• Vcap Submodule Capacitor Voltage
• Vdc dc bus pole to pole voltage

Implementing MMC Model in FPGA

• Small SM time step
  
  • (number of capacitors per valve*1.25) ns
  • E.g. 250 ns for valves with 200 half bridge or full bridge SM
  • Sub microsecond for valves with less than 800 Capacitor
• Large number of SM
  
  • up to 1000 SM per valve (6000 SM per converter) in standard bitstream
  • Scalable for more than 1000 SM per valve upon request
• MMC VBC (low level controller) and communication protocol are implemented in same FGPA
  
  • Advanced VBC works for 1000 SM per valve
  • Driver for 16 SFP (5 Gbits /s) with Gigbit protocol
• Support multiple FPGAs for HVDC grids

Principle: Multi-Rate MMC Modelling

T_cpu = tens of microsec, T_FPGA = sub miscrosec

Inside FPGA

Routing Inside FPGA

In MMC valve model side

• K1: switch for gating signal at MMC valve input
  
  • From local (VBC or CPU)
  • From external (fiber optical or IO)

In VBC side

• K2: switch for gating signal at VBC output
  
  • From CPU
  • From embedded VBC
• K3: for SM measurements switch at VBC input
  
  • From local MMC model
  • From external (fiber optical or IO)

Digital Simulation: Valve Control Implemented in CPU

Digital Simulation: Valve Control Implemented in FPGA

HIL Application: Connecting to Actual Controller

RCP Application: Connecting to MMC System

HIL Application: Two Independent Targets

RT-LAB MMC Blocks in Library

• MMC library has to be installed
  
  • Currently eFPGAsim also has to be installed
• User can type “libMMCcpuv2” in the Matlab command window to open the MMC sub library.
  
  • In the future versions, it will be linked to the Simulink library browser.
• Blocks used in MMC FPGA models
  
  • MMC parameters
  • Fault set
  • MMC pulse
  • FPGActrl
  • FPGAValve

MMC Blocks at a Glance

Typical Model Configuration

Typical Model Configuration: Block Connection

MMC Parameters Block

• GUI to configure MMC valve and control parameters.
• Placed in the console ( sc_subsystem)
• no input and 1 output by BusCreator
• Most the parameters can be changed during simulation
• There are 8 tabs in its parameter mask
  
  • Parameters: MMC parameter configuration
  • Operation: MMC operations setting
  • Controller: internal controller configuration
  • Protection: protection configuration
  • Scope: monitoring setting
  • Advanced: advanced configuration
  • Parameter discrepancy: for SM C and discharge R discrepancy setting
  • Fault: MMC SM fault pattern
• User can click “Help” button for more information

• SM type of group (1, 2, 3): One MMC valve can have up to 3 types of SM. It sets SM type for each group. Options of SM type are
  
  • 0: Half-bridge
  • 1: Full-bridge
  • 2: Clamped-double
  • 3: T-type SM
• number of SM in group (1, 2, 3): number of SM in group (1, 2, 3) in one valve.
• SM are numbered in ascending order of groups. For example of right figure, SM0~9 are HB SM, SM10~14 are FB SM, SM15~24 are CD SM.
• Total SM number should ≤ allowed by license.
• Total capacitor number is ≤ 1000 in standard bitstream, but can be expended at request.
• If one valve has only 1 or 2 SM types, SM type of group 2 or 3 can be disabled.

• Cell capacitance design value (farads): capacitance of each cell capacitor in Farad.
• Switch Ron (ohms): IGBT switch ON resistance in ohm.
• SM capacitor normal and fast discharge resister design value [ohms] ( eg . [2200 200] Resistance in ohm of the normal and fast discharge resistors in parallel with the SM capacitor. Please also refer to “fast discharge” in Operation tag.
• [Sb Vb ]Power and voltage base (VA, V, 1 phase): MMC power rating and dc pole pole voltage, used to per unitized MMC voltages, currents, and powers.
• gating signal dead time ( μs), maximum 50 μ s : dead time of IGBT pair (e.g. G1 and G2 in HB SM) in μs.

MMC Parameters Block: Operation Tab

• Enable pulse: enable pulse applied to IGBT, otherwise, all IGBT are blocked.
• g5 (CDSM) or force bit (g3=0, g4=1 in FBSM): For SM of CDSM type, It sets G5 On when enabled or G5 Off when disabled. For SM of FBSM type, it overrides G3 and G4 signals and forces G3 On and G4 Off (normally for charging period of FBSM). Options are
  
  • 0: disable
  • 1: enable
  • 2: by protection signal
• fast discharge: if unchecked, only normal discharge resistor is inserted; and if checked only fast discharge resistor is inserted. It applies to all SM.

• Vcap mode: determines how SM capacitor voltage is calculated in FPGA. options are
  
  • 0: normal operation
  • 1: Vcap reset to 0
  • 2: Vcap use average value
  • 3: Vcap reset to fix value

Always select “0: normal operation” for normal simulation mode, where SM capacitor voltage respects physical law, i.e. calculated by the charging current and capacitance. The other modes are for debugging purposes, where SM capacitor voltage doesn’t respect physical law.

• Vcap mode: determines how SM capacitor voltage is calculated in FPGA. options are
  
  • 0: normal operation
  • 1: Vcap reset to 0
  • 2: Vcap use average value
  • 3: Vcap reset to fixed value

Option “1: Vcap reset to 0” forces all SM capacitor voltages to zero. It can be used to initialize the system.

Option “ 2: Vcap use average value ” is under development.

Option “ 3: Vcap reset to fixed value ” forces to all SM capacitor voltages to a fixed value given in the next parameter “ Vcap fixed value (p.u.)”. This mode emulates system performance when applying an ideal capacitor voltage control.

MMC Parameters Block: Operation Tab

• Force cap charge current to zero: When checked, capacitor charging current for Vcap calculation is considered to be zero regardless of actual current value. This option is only for debugging mode and should not be checked in normal simulation.
• MMC gating signal routing: corresponding to selector K1 in page 7. It determines SM gating signal source, local from imbedded control in same FPGA or external through IO/SFP.
  Options are:
  
  • 0: internal
  • 1: external from SFP
• For MMC, measurement message interval (μs): interval in μs of MMC measurement (e.g. V_cap, I_arm, etc ) packets being sent out to internal or external controller.

• enable protocol port : enable(checked) or disable (unchecked) signals being sent through
  gating signal from: corresponding to selector K2 in page 7. It sets gating signal source in controller, either generated in CPU and sent to FPGA or generated by controller in FPGA.
  Options are
  
  • 0: gate signal from CPU
  • 1: embedded VBC in FPGA
• CPU gating signal mode: related (unchecked) /full ( checked): determines which gating signals sent from CPU to FPGA. In related mode, Only g1 in HB SM, or g1 & g3 in FB, CD, T SM are sent. For HB, FB, CD SM, g2=NOT(g1), g4=NOT(g3); for T SM, g2=NOR(g1,g3), g4=g3. In full mode, all gating signals are sent. Refer to “MMC pulse” block also.

• In controller, measurement from protocol (check)/local ( unchecked): corresponding to selector K3 in page 7. It determines SM measurement source for embedded controller, either from protocol (if checked), or from local SM through internal wiring (if unchecked).
• carrier frequency (Hz), max 3000Hz, resolution 0.05Hz: PWM carrier frequency to generate IGBT gating signal by embedded controller.

• Command packet interval by controller (us) interval in μ s of controller command (e.g. gating signals etc.) packets being sent by embedded VBC to internal or external MMC valve.
• inverse current direction at protocol (positive for charging(unchecked) or discharging (checked): In MMC measurement packet, positive current direction is defined as charging SM capacitor if this option is not checked. Otherwise, positive current discharge SM capacitor.

MMC Parameters: Protection Tab

• Overvoltage protection level (1, 2) enabled: SM capacitor overvoltage detection level (1, 2) is enabled if checked or disabled if unchecked.
• Overvoltage threshold (1, 2) (pu), maximum 4 pu: threshold for overvoltage protection level (1, 2). If capacitor voltage exceeds this value, overvoltage level (1, 2) signal becomes True.
• Overvoltage protection (1, 2) latch: Allows overvoltage level (1, 2) signal being latched if checked. Once latched, the overvoltage signal keeps True even Vcap reduces below the threshold. To reset latched signal, this option has to be unchecked and Vcap is below the threshold.

• Undervoltage protection enabled: SM capacitor undervoltage detection is enabled if checked or disabled if unchecked.
• Undervoltage threshold: threshold for undervoltage protection. If capacitor voltage goes below this value, undervoltage signal becomes True.
• Undervoltage protection latch: Allows undervoltage signal being latched if checked. Once latched, the undervoltage signal keeps True even Vcap recovers beyond the threshold. To reset latched signal, this option has to be unchecked and Vcap is exceeding the threshold.

• Overvoltage and undervoltage signals are for individual SM and can be used for various SM protection schemes.
• In standard bitstream, Overvoltage level 1 signal is used in imbedded SM protection, i.e. if it is True in an SM, that SM will override input gating signal and be bypassed immediately.
  Overvoltage level 2 and undervoltage signals are not associated to imbedded SM protection.
  However, they are sent to controller, and controller could response to them and apply proper protection by sending back commands to SM.
• More complicated imbedded SM protection scheme is possible at request. Or users could build their own after advanced training.

MMC Parameters Block: Scope Tab

• Receiving packet interval(us): instant(checked) or maximum (unchecked) value : This option sets if interval of receiving packet of controller and SM is in instantaneous or maximum value. Unit is µs, with resolution of 0.16 µs and range of 163.7 µs. It is useful to debug communication protocol between controller and SM in HIL tests. For example, if controller is designed to send command packet every 20 µs, MMC receiving packet interval should read 20 µs. If it has maximum value of 60 µs, it means that for some instance, MMC didn’t receive command packet in time as expected. Further investigate is required to see if the problem is at controller side or protocol side.

• Vcap measuring point at valve(unchecked)/ vbc ( checked): SM capacitor voltages and states are sent to CPU model and output at “ FPGActrl ” block out port “info” (refer to FPGActrl block in the slices). This option sets if above measurements are measured at MMC valve or at embedded VBC. Note if SM states are not sent to VBC and measuring point is at VBC (option checked), SM states displayed at CPU will be random value.
• View SM state : If checked, this option enables SM states being sent to CPU for display.
• View SM state on : This option selects of which valve SM states being sent to CPU for display.

• SM number for display (for input=N, 2N*6 SM for Vcap , 2N SM for state): This option sets number of SM, of which measuring info is sent to & displayed in CPU. If value is N, Vcap of 12N SM (2N per valve) and states of 2N SM are sent. Note it has same value as parameter in block FPGActrl
• SM selection offset (for input=x, SM: 2x is 1 st being displayed): This option sets which SM in a valve is the 1 st SM being displayed.
• For example: if in above options N=10 & x=2, Vcap of SM4~23 of valves 0~5 (120 Vcap ) are sent to CPU. If further “View SM state” is checked and “View SM state on”=“valve 0”, states of SM4~23 of valves 0 are also sent to CPU.

• Valve info: showing: this option shows different debugging information comes from the valves
  
  • 0: Vcap max min values: if this is selected, look at the corresponding monitoring block in the console, it displays maximum and minimum Vcap values in each valve.
  • 1: total SM number that: if this option is selected, another selection to choose total SM number that
    0: g1 is ON; 1: g2 is ON; 2: g3 is ON and 3: g4 is ON will be available. Choose one of the options and the corresponding results will be displayed. There will also be a checkbox to choose if instant or maxmin value will be shown.
  • 2: valve state and choose the option according to the following table.

• SM state summary
  
  • In FPGA model, each SM has an internal 16 bit state as below.
  • Original SM state info of selected SM is displayed as explained in previous pages.
  • This option allows to display selected summary of SM state in a valve. Please refer to “ FPGActrl ” block.

• Controller info : showing: this option allows to see the debugging information in the controller
  
  • 0: total inserted SM number: the total number of inserted SM in the controller
  • 1: reserved
  • 2: reserved
  • 3: reserved

MMC Parameters Block: Advanced Tab

• Check to show advanced options (for advanced user only): parameters in this tab should keep default values and can modified only by advanced user. Check this item to show the options and verify that default values are used as listed below.
• Time step at cpu model (s) s): By default it uses variable “ Ts ” which should be defined as CPU model time step in second in initial file.
• FGPA clock (fixed for bitstream) bitstream): 5ns by
• Minimum number of FPGA clock per cycle : 20 by default.
• Vmmc average over TsCPU ( check)/inst value (uncheck) checked by default.
• Current sync mode : checked by default.
• Current correction mode : mode 1 by default

MMC Parameters Block: Parameters Discrepancy Tab

• If capacitor or discharge resister in SM i has value (x_ i ) different than designed value (x_d ) in tag “parameter”, discrepancy is defined as disc_ i = x_d / x_ i 1
  • example: if designed SM capacitance is 5mF,
  • for SM 1, cap=4mF, disc_1=0.25,
  • for SM 2, cap=5mF, disc_2=0,
  • for SM 3, cap=6mF, disc_3= 0.1667
• parameter discrepancy range : set range for discrepancy data. Options are
  
  • 0: no discrepancy
  • 1: max error +/ 1pu; resolution 0.78%
  • 2: max error +/ 0.5pu; resolution 0.39%
  • 2: max error +/ 0.25pu; resolution 0.20%.

For above example.

• parameter discrepancy data : data for discrepancy patterns, a matrix variable “ paradisc ”. Variables dimen_paradisc ” and depth_paradisc ” are number of rows and columns of “ paradisc ” and set in mask of FPGActrl ” block, should not change after compilation. 3 variables are predefined in initial file MMCparameterdiscrepancy.m
  
  • dimen_paradisc is number of patterns, ≤12;
  • depth_paradisc is number of discrepancy data in one pattern.
• discrepancy pattern of SM Capacitance/ discharge R in valve (0~5) 5): to apply selected discrepancy pattern on SM C or R of valve (0~5), options are
  
  • 0: no discrepancy
  • 1~12: parameter discrepancy pattern 1~12
  • If pattern number> dimen_paradisc, no discrepancy applied.
  • If number of Cap> depth_paradisc, discrepancy applied to first depth_paradisc number of C/R; others have designed value (no discrepancy).

MMC Parameters Block: Fault Tab

• Users can apply or clear specific faults set in “Fault” tab on selected SM set in “fault set”
• clear temporary fault (checked) checked): If not checked, all SM faults will be latched. If checked, all currently non-active faults will be cleared.
• set fault : drop off list to specify if specified fault set is applied with one of options:
  
  • 0: no fault
  • 1: fault on valve 0 only
  • 2: identical fault on all valves
  • 3: fault on different valves

• Fault0 on Valve0: select fault 0 on valve 0 and define it in “Fault set” block
• Fault1 on Valve0: select fault 1 on valve 0 and define it in “Fault set” block
• Fault2 on Valve0: select fault 2 on valve 0 and define it in “Fault set” block
• If select 3: fault on different valves in the option “set fault”, the same three checkboxes will display for different valves

MMC Fault Set Block

• GUI, placed in the console subsystem , defines up to 4 selections of SM. It works with “ MMC parameter\ fault”, to apply or clear specific faults on these SM selections
• No input and 1 out port with multiplexed signals.
• 4 tabs “SM group”, “fault0”, ”fault1”, “fault2”
• Users define SM group of fault selection in the first tab and select fault types of fault groups in the other three tabs.
• Parameters can be changed during simulation. It is also possible for advanced user to generate the SM selections in an interactive style with power system during simulation.
• User can click “Help” button for more information and refer to MMC Parameter block help file.

• SM group Tab: select different SM groups with different fault pattern, users can select 3 different fault patterns. 3 SM groups have the same selections.
• selecting method : options are
  
  • 1:selection by starting # and # of SM
  • 2:selection 20 SM by bit set with offset
  • 3:select all
  • 4:select none
  • Options 1 and 2 works with other parameters explained in next pages. Option 3 means all SM in valve are selected. Option 4 means no SM is selected.

• [starting #, # of cell]: works with selecting method "1:selection by starting # and # of SM”. First parameter is the number of first selected SM. Second parameter is the total number of selected SM.
• Note first SM in a valve is numbered as SM 0.
  
  • Example 1, [0 5] means that selection includes
  • SM0 ~ SM4, total 5 SM.
  • Example 2, [5 3] means that selection includes
  • SM5, SM6, SM7, total 3 SM.

• select 20 SM by bitset : works with selecting method “ 2:selection 20 SM by bit set with offset”. 20 parameters with value either 1 or 0 represent 20 consecutively numbered SM being selected or not.
• offset: input N and above selection is offset by 4*N : works with selecting method “ 2:selection 20 SM by bit set with offset”. Parameter multiplied by 4 gives offset of above selection of 20 SM.
• Note first SM in a valve is numbered as SM 0. Example 1, bitset =[1 1 0 0, 0 0 0 0, 0 0 0 0, 0 0 0 0, 0 0 0 1 ], offset=0 means that selection includes SM0, SM1, SM19, total 3 SM.
  Example 2, bitset =[1 1 0 0, 0 0 0 0, 0 0 0 0, 0 0 0 0, 0 0 0 1 ], offset=3 means that selection includes SM12, SM13, SM31, total 3 SM.

MMC SM Fault Set Example

Example 1: apply G1 open circuit fault on {SM5, SM6, SM7, SM12, SM13, SM31} in valve0:

• Go to the tab “MMC Parameters/fault”, Select fault to be “fault on valve 0 only”, check the box “Fault 0 on valve 0”.
• In “Fault_set” block, in “SM group” tab, use SM group 0, select “1: starting # and # of SM ”,then “[starting #, # of cell]”=[5 3], SM group 0 includes SM 5, SM 6 and SM 7. In the parameter for SM group 1, select “by bit set with offset” bitset=[1 1 0 0, 0 0 0 0, 0 0 0 0, 0 0 0 0, 0 0 0 1 ], offset=3. SM group 1 includes SM12, SM13, SM31.
• In “Fault 0” tab, make “Apply (check) or remove (uncheck) fault” checked, of “1: g1 fault”, make the box “open circuit (uncheck) or short circuit (check) fault” unchecked.
• Check the boxes “on SM group 0” and “on SM group 1”

Example 2: continue from example 1, clear G1 open circuit fault on {SM12, SM31} in valve0: In “MMC parameter” block, “fault” tab, uncheck “clear temporary fault”, thus G1 open circuit fault on {SM5, SM6, SM7, SM12, SM13, SM31} in valve0 are latched. Go to the tab “MMC Parameters/fault”, check the box “Fault 1 on valve 0”.

• In “ Fault_set ” block, “Fault 1” tab, change bitset =[1 0 0 0, 0 0 0 0, 0 0 0 0, 0 0 0 0, 0 0 0 1 ], offset=3. Fault 1 includes SM12, SM31.
• Uncheck “adding (checked) or removing (unchecked)”. Thus G1 open circuit fault on {SM12, SM31} in valve0 is cleared.

Example 3: continue from example 2, clear all fault on all SM in valve0:

• In “MMC parameter” block, “fault” tab, check “clear temporary fault”,
• “set fault”= “0: no fault”; or uncheck all the boxes for fault on valve 0 or In “ Fault_set ” block, in 3 “Fault x” tab, uncheck “adding (checked) or removing (unchecked)”.

MMC Fault Set Block

• Fault0~fault2: 3 tabs to define different fault patterns
• Apply (checked) or remove (unchecked) fault : If checked, fault specified in MMC parameter block will be applied to SM in selection. If unchecked, fault specified will be cleared.
• Of:
  
  • 1: g1 fault: fault on g1
  • 2: g2 fault: fault on g2
  • 3: g3 fault: fault on g3
  • 4: g4 fault: fault on g4
  • 5: capacitor short circuit fault: SC fault on capacitors
• Open circuit (unchecked) or short circuit (checked) fault: when select first 4 options, this option will appear to select if the fault is open circuit or short circuit
• On SM group 0~on SM group 2: 3 options to select which fault patterns will be applied as defined in the tab “SM group”. Users can select up to 3 patterns at the same time. For example, check the box “on SM group 0” in the tab “fault 0”, the fault pattern defined in the tab “SM group  SM group 0 ” will be applied as “fault 0” and the valves who selected fault 0 on “MMC Parameters/fault” will have the faults.

MMC Pulse Block

• GUI, placed in console subsystem, to manually set gating signals, being sent from CPU to FPGA.
  
  • Updating rate is CPU time step
• no input and one multiplexed output port.
  
  • Output has 8*6 32-bit signals, each contains 32 gating signals.
• Six taps “Valve(0~6)” in parameter mask with same options, each corresponding to one of 6 MMC valves.
• Two modes for gating signal being sent to FPGA, as set in “MMC parameter” block, option “\controller\CPU gating signal mode”
  
  • Full mode: option checked, signal for all gating signals are sent. (g1 & g2 for HBSM, g1~g4 for FB, CD, T-SM.)
  • Related mode: option unchecked. Only g1 for HB-SM and g1 & g3 for FB, CD, TSM are input. g2=NOT(g1), g4=NOT(g3) in HB, FB, CD-SM; g2=NOR(g1,g3), g4=g3 in T-SM.
• User can click “Help” button for more information.

MMC Pulse Block: HB SM (Related Mode)

• For HB SM and in gating signal “Related mode”, each parameter, taking value either 0 or 1, represents G1 being Off or On. G2 is inverse of G1.
• Gate signal group (0~7) 7): each line can input 32 signals for G1 of 32 SM. SM are numbered in ascending order.
• Example: as in the figure, G1 is On in {SM0, SM9, SM18, SM27, SM32, SM41, SM50, SM59} and Off in other SM

MMC Pulse Block: HB SM (Full Mode)

• For HB SM and in gating signal “full mode”, both G1 and G2 are set by parameter, taking value either 0 or 1, represents Off or On state.
• Gate signal group (0~7) 7): each line can input 32 signals for 16 SM. First 16 for G1 and last 16 for G2. SM are numbered in ascending order.
• Example: as in right figure, G1 is On in {SM0, SM9, SM16, SM25} and Off in other SM; G2 is On in {SM2, SM11, SM18, SM27} and Off in other SM.

MMC Pulse Block: FB, CD, T-SM (Related Mode)

• For FB, CD, T SM and in gating signal “Related mode”, G1 & G3 are set by parameter. G2 & G4 are determined by G1 & G3.
• Gate signal group (0~7) 7): each line can input 32 signals for 16 SM. First 16 for G1 and last 16 for G3. SM are numbered in ascending order.
• Example: as in right figure, G1 is On in {SM0, SM9, SM16, SM25} and Off in other SM; G3 is On in {SM2, SM11, SM18, SM27} and Off in other SM.

MMC Pulse Block: FB, CD, T-SM (Full Mode)

• For FB, CD, T SM and in gating signal “full mode”, G1 G4 are set by parameter.
• Gate signal group (0~7) 7): each line inputs 32 signals for 8 SM. 4 groups of 8 signals are for G1, G2, G3, G4 respectively. SM are numbered in ascending order.
• Example: as in right figure, G1 is On in {SM0, SM8} and Off in other SM; G2 is On in {SM1,SM9} and Off in other SM; G3 is On in {SM2, SM10} and Off in other SM; G4 is On in {SM4, SM11} and Off in other SM;.

MMC Pulse Block

• gating signal “ related mode” means SM works at normal operation with pulse enabled. “ Full mode ” includes all possible gate state combinations, which can represent SM in states of pulse disabled, deadtime, abnormal, or fault conditions.
• Each line of 32 0 or 1 inputs is converted to one UFIX32.0 signal in ascending order, i.e. first input is in LSB.
• This block allows 8 lines (32*8 inputs) for each valve, thus for 6 valves it outputs 8*6 UFIX32.0 signals, which are interleaved, i.e. first signal is for valve0, 2 nd signals is for valve 1, … , 7 th signal is for valve 0, as in table.
• Parameters may change during simulation. Advanced user can generate gating signal from controller in CPU. Gating signal is connect to “ FPGActrl ” block input “

FPGActrl Block

• This block, usually placed in control subsystem,
  
  • receives MMC parameters, control, and gating signals;
  • communicates with VBC and SM models in FPGA;
  • outputs SM measurements and monitoring signals
• 5 inputs:
  
  • ref: Vmmc reference voltage from control, sent to VBC in FPGA. Range: ( 1,1) for FB SM, [0,1) for HB and CD SM. Dimension: 6, for 6 valves.
  • ebl: gating signal enable. Value: 0(disable) or 1(enable). Dimension: 1 (same for 6 valves) or 6(for individual valves). It can connect to signal manually set in MMC Parameters block, or signal pre defined or interactive with controller.
  • para: All parameters set in MMC Parameters block.
  • gate: The gate signals either from MMC Pulse block or from the controller.
  • g5: g5 for CDSM or force bit (forcing g3=0, g4=1) for FBSM. Dimension: 1
    (same for 6 valves) or 6(for individual valves).

• 3 outputs:
  
  • Vcapave_pu: average capacitor voltage in per-unit value. Dimension: 6, for 6 valves. Updated at every Ts
  • VIbase: parameters sent to MMC FPGAValve block, including voltage and current bases and number of capacitor.
  • Info: SM measurements and monitoring signals as figure in right:
• User can click “Help” button for more information.

FPGActrl Block: Mask

• FPGA Controller Name: name of controller, must be same as the defined in OpCtrl or OpLnk block.
• Converter #: controller ID, start from 0, unique for controller in same FPGA. maximum number is limited by specific FPGA bitstream. For one MMC converter, converter ID in “ FPGActrl ” block and FPGAvalve ” block should be
• Number of Valves : number of valves used in this converter. Maximum 6. Typically 6 for one AC/DC converter, 3 for STATCOM. Total number of valves in all converters is limited by user MMC license “XSG_MMC_VALVES”
• maximum # of cell per valve in license : maximum number of SM per valve defined in user license “XSG_MMC_CELLS_PER_VALVE”. Actual number of SM per valve should be ≤ this value.

• gating signal dimension ( Ngin )): number of gating signals being set to FPGA. Sending gating signal to FPGA takes CPU time. Thus input minimum value to avoid sending unused gating signals. Example, for MMC with 50 HBSM in a valve, enter 12 for related mode and 24 for full mode.
• SM number for display (same value in MMC parameter block, Nvc ): This option sets number of SM, of which measuring info is sent to & displayed in CPU. If value is N, Vcap of 12N SM (2N per valve) and states of 2N SM are sent. Note it has same value as parameter in block “ MMC parameter scope ””.
• CR discrepancy pattern number : default value is variable dimen_paradisc
• number of CR discrepancy data in one pattern : default value is variable depth_paradiscdata
• dimen_paradisc ” and depth_paradisc ” are number of rows and columns of “ paradisc ” and set in block FPGActrl CR discrepancy”. 3 variables are predefined in initial file MMCparameterdiscrepancy.m
  
  • dimen_paradisc is number of patterns, ≤12;
  • depth_paradisc is number of discrepancy data in one pattern.
• Above 4 parameters cannot change once model is compiled.

FPGActrl Block: Output Info

• Out port Info: by bus creator, containing signals (dimension):
  
  • info ctlinfo (12): for VBC debugging;
  • info vlvinfo (12 ): showing: this option shows different debugging information comes from the valves, please refer to previous slices of MMC Parameters/Scope;
  • info Interval (2 ): interval of signal packet between VBC and valve;
  • Vc (Nvc *12): Capacitor voltages in PU, Nvc *2 per valve and 6 valves.
  • st (Nvc ): Nvc number of SM states for selected valve.
• "Nvc ” is variable defined in initial file and input as parameter in “ FPGActrl ” block mask

• info ctlinf o (12 ): for debugging of embedded
  
  • First 6 signals: total number of SM with G1 being On in reference of VBC input.
  • Last 6 signals: total number of SM with G1 being On in gating signal of VBC output.
• info\ vlvinf o 12): 0: max & min Vcap of each valves
  
  • First 6 signals: minimum capacitor voltages in each valves.
  • Last 6 signals: maximum capacitor voltages in each valves.
• 1: total SM number that (with
  
  • First 6 signals: total specified SM number (e.g. G1 is on).
  • Last 6 signals : complementary of the first 6 signals (e.g. G1 is
• 2: SM states info (TB continued)
  
  • First 6 signals: the states of each valve respectively.
  • Last 6 signals: the number of SM in each state.
• SM states info
  
  • 1 signal for 1 valve in ascending order (e.g. 1 st signal for valve 0).
  • In FPGA model, each SM has an internal 16 bit state
  • Providing SM information according to option in block MMC_parameter scope SM state summary” as in table

• Example: SM3 has G1,G2 open circuit fault; SM5, SM7 have G2 open circuit fault; SM 10~14 undervoltage, no fault in other SM:
  
  • if “summary option” is “0: bit 0”, “state”=1; (SM3)
  • if “summary option” is “2: bit 2”, “state”= 3; (SM3,5,7)
  • if “summary option” is “12: bit 12”, “state”= 5; (SM10~14)
  • if “summary option” is “16: bit any”, “state”= 8; (SM3,5,7,10~14)
  • if “summary option” is “17: bit”, “state”= {0001 0000 0000 0101} b ;
  • if “summary option” is otherwise, “state”= 0.

• info Interval (2): interval of signal packet between VBC and valve
  
  • First 1 signal: interval of control measurement packet sent to MMC.
  • Last 1 signal: interval of MMC command packet sent to VBC.
• For above signals, 1 signal for 1 valve in ascending order (e.g. 1 st signal for valve 0).

• Vc (Nvc *12): Capacitor voltages in PU, Nvc *2 per valve and 6 valves.
  
  • Dimension is determined by variable “ Nvc ” defined in initial file and input as parameter in “ FPGActrl ” block mask. Nvc ” cannot change once model is compiled.
  • Nvc *2 signals for each valve. First signal is for n th SM defined in block MMC parameter scope offset of Vcap ” in ascending order.
  • Total Nvc *12 signals for 6 valves in ascending order, e.g. 1 st group of Nvc *2 signals for valve 0.
  • Example, if “ MMC parameter scope offset of Vcap ”=2, Nvc =10; Vc has 120 signals. The first 20 signals are Vcap of SM4~23 in valve 0.
• st (Nvc ): Nvc number of SM states for selected valve.
  
  • Dimension is determined by variable “ Nvc ” defined in initial file and input as parameter in “ FPGActrl ” block mask. Nvc ” cannot change once model is compiled.
  • Each signal has 32bit, displaying states of 2 SM. Each SM has 16bit states defined in SM internal state table in previous page.
  • Nvc number signals for valve defined in block MMC parameter scope select to view SM state on which valve”;
  • First signal is for n th SM defined in block MMC parameter scope offset of Vcap ” in ascending order.
  • Example, if in “ MMC parameter scope”, which valve”=“0”, “offset of Vcap ”=2, Nvc =10; Vc has 10 signals, for states of SM4~23 in valve 0.
• Signals Vc and st are either from valve or VBC, depending on option “ Vcap measuring point” in “MMC parameter” block.

FPGAValve Block

• “FPGAValve” block, usually placed in grid subsystem, couples grid model in CPU and MMC valve model in FPGA:
  
  • Sending valve currents to FPGA
  • Receiving valve voltages from FPGA
• 2 inputs:
  
  • MMCpara: parameters from MMC FPGActrl block, including voltage and current bases and number of capacitor.
  • Iarm: valve currents, positive currents direction defined as going out of o1 (please also refer to MMC Interface block help file). Dimension: 6.
• 1 output:
  
  • Vmmc: Vmmc signals, Dimension: 12 for 6 MMC values, 2 for each valve.
• User can click “Help” button for more information.

FPGAValve Block: Mask

• FPGA Controller Name: name of controller, must be same as the defined in OpCtrl or OpLnk block.
• Converter #: controller ID, start from 0, unique for MMC valve in same FPGA. maximum number is limited by specific FPGA bitstream. For one MMC converter, converter ID in “ FPGActrl ” block and FPGAvalve ” block should be
• Number of Valves : number of valves used in this converter. Maximum 6. Typically 6 for one AC/DC converter, 3 for STATCOM. Total number of valves in all converters is limited by user MMC license “XSG_MMC_VALVES”
• maximum # of cell per valve in license : maximum number of SM per valve defined in user license “XSG_MMC_CELLS_PER_VALVE”. Actual number of SM per valve should be ≤ this value.

• Gating signal dimension ( Ngin ): number of gating signals being set to FPGA. Sending gating signal to FPGA takes CPU time. Thus input minimum value to avoid sending unused gating signals. Example, for MMC with 50 HBSM in a valve, enter 12 for related mode and 24 for full mode. Cannot change once model is compiled
• SM number for display (same value in MMC parameter block, Nvc ): This option sets number of SM, of which measuring info is sent to & displayed in CPU. If value is N, Vcap of 12N SM (2N per valve) and states of 2N SM are sent. Note it has same value as parameter in block "MMC parameter scope". Cannot change once model is compiled
• CR discrepancy pattern number : default value is variable dimen_paradisc ". Cannot change once model is compiled
• number of CR discrepancy data in one pattern : default value is variable " depth_paradiscdata ". depth_paradisc " is the number of column and set in block " FPGActrl CR discrepancy". Cannot change once model is compiled.

MMC Model Demos

The user can find 5 demos in the folder C:\ OPAL-RT\ MMC\ %Version#%\ Examples

• MMC HVDC CPU demo:
  Folder: C:\OPAL-RT\ MMC\% Version#%\ Examples\ MMC4_ cpu_HVDC\ Simulink
  This demo is a half-bridge MMC HVDC system in CPU.
• MMC STATCOM CPU demo:
  Folder: C:\OPAL-RT\ MMC \% Examples MMC4_cpu_STATCOM Simulink
  This demo is a full bridge MMC STATCOM system in CPU.
• MMC HVDC FPGA demo:
  Folder: C:\OPAL-RT\ MMC\% Version#%\ Examples\ MMC6 _ HVDC\ Simulink
  This demo is an MMC HVDC system in FPGA.
• MMC STATCOM FPGA demo:
  Folder: C:\OPAL-RT\ MMC\% Version#%\ Examples\ MMC6 _fpga_ STATCOM\ Simulink
• MMC FPGA Unitary test demo:
  Folder: C:\OPAL-RT\ MMC \% Examples\ MMC6_fpga_unitary\ Simulink
  This demo is a unitary test demo for MMC FPGA model