Library

ARTEMiS/SSN/Inverters

Blocks

Description

These blocks implement 2-level models within the SSN-IVIC interpolation algorithm. IVIC stands for Inlined Voltage Inverter Compensation and is an SSN algorithm that compensates for firing events occurring within a simulation time step. SSN-IVIC is similar to SSN-ITVC algorithm for thyristors.

The 2-level inverter comes in 1-phase, 2-phase and 3-phase versions.

These models can be substituted in many cases with the most recent generation of Time-Stamped Bridge (TSB) called TSB-RD, RD standing for Real Diodes. These TSB supports interpolation methods like IVIC but behave a better typically when the PWM frequency get high (i.e, Fpwm>0.1/Ts).

Dead-time support

SSN-IVIC supports dead-time smaller than simulation time step (as opposed to SPS inverter models).

 2-level inverter

Masks

Parameters

Snubber resistance (ohms): the snubber resistance in ohms.

Snubber Capacitance (F): the snubber capacitance in Farads.

Ron (Ohms): the switch conduction resistance in Ohms.

Forward voltages: switch forward voltages in Volts. Note that this parameter cannot be set to 0 because it is used internally by the IVIC algorithm.

[Tf(s), Tt]: not used in IVIC.

Input and Output signals

Simulink connection points

g: the IGBT/GTO/MOSFET gate input signals. The order of the gate signal for phase A is S1, S2 as indicated in Figure 1. Phase B and C are following.

Physical Modeling connection points

A,B,C: inverter outputs for phases A,B and C.

+, -: DC-bus connection points.

Examples

This model is used in the ‘ARTEMiS-SSN Inlined Time-Stamped Bridge in 2-level VSC-based HVDC applications using IVIC algorithm(SSN)’

References

C. Dufour, J. Mahseredjian , J. Bélanger, “A Combined State-Space Nodal Method for the Simulation of Power System Transients”, IEEE Transactions on Power Delivery, Vol. 26, no. 2, April 2011 (ISSN 0885-8977), pp. 928-935