Library

ARTEMiS/SSN/Inverters

Blocks

Description

These blocks implement 3-level NPC (Neutral-Poiont-Clamped) models within the SSN-IVIC interpolation algorithm. IVIC stands for Inlined Voltage Inverter Compensation and is an SSN algorithm that compensates for firing events occurring within a simulation time step. SSN-IVIC is similar to SSN-ITVC algorithm for thyristors.

The 3-level NPC inverter comes in 2 flavors, the most recent being v2.0. The 2 inverters have similar characteristics but implement the IVIC algorithm differently in the code. The v2.0 uses an external S-function while the other is embedded in the main SSN solver.

These models can be substituted in many cases with the most recent generation of Time-Stamped Bridge (TSB) called TSB-RD, RD standing for Real Diodes. These TSB supports interpolation methods like IVIC but behave a better typically when the PWM frequency get high (i.e, Fpwm>0.1/Ts).

Dead-time support

SSN-IVIC supports dead-time smaller than simulation time step (as opposed to SPS inverter models).

In particular, the v2.0 model can be made to simulate cases with firing pulse shorter that the simulation time, even in offline mode. Details can be seen in the demo ‘ARTEMiS Three-Level NPC inverter simulation with compensation of switching events using Inlined Time-Stamped Bridge(SSN)’ in the on-line demo section of ARTEMiS-SSN.

3-level NPC inverter

Masks

Parameters

Snubber resistance (ohms): the snubber resistance in ohms.

Snubber Capacitance (F): the snubber capacitance in Farads.

Ron (Ohms): the switch conduction resistance in Ohms.

Forward voltages: switch forward voltages in Volts. Note that this parameter cannot be set to 0 because it is used internally by the IVIC algorithm.

High impedance current tolerance (A) (v2.0 only): this parameter is used by the IVIC algorithm when to consider the inverter in high-impedance mode. This sets a current limit under which, when all gates are OFF effectively push the inverter in high impedance mode. It should be set to a value that is considered negligible, depending on the application and power ratings of the simulated device.

Input and Output signals

Simulink connection points

g: the IGBT/GTO/MOSFET gate input signals. The order of the gate signal for phase A is S1, S2, S3, S4 as indicated in Figure 1. Phase B and C are following.

Physical Modeling connection points

A: inverter output

+,N, -: DC-bus connection points.

Examples

This model is used in the ‘ARTEMiS Three-Level NPC inverter simulation with compensation of switching events using Inlined Time-Stamped Bridge(SSN)’

References

C. Dufour, J. Mahseredjian , J. Bélanger, “A Combined State-Space Nodal Method for the Simulation of Power System Transients”, IEEE Transactions on Power Delivery, Vol. 26, no. 2, April 2011 (ISSN 0885-8977), pp. 928-935