Sample Time (s)

Sets the sample time for the fixed time step simulation of the electrical part of the SPS model. This sample time should be the same as the one entered in the SPS PowerGUI block.

Enable State-Space Nodal method

When checked, activates the use of SSN methods and solver in all SPS circuits. Since 7.2.1, this also applies to SPS circuits that do not have Nodal Interface Blocks (NIB), the circuit is considered as a 1-group SSN circuit, using the SSN solver.

State-Space discretization method

Sets the discretization method used by the ARTEMiS algorithm for the normal state-space system, not the one using the SSN method.

Four different methods are available: art5 (default), art3, art3hd and trapezoidal.

The art5 and art3 discretization methods are highly stable and very-accurate integration methods. Both are immune to numerical oscillations caused by switch operations in power networks. The art5 method is theoretically more accurate than art3, as it approximates the matrix exponential Taylor expansion to the 5th term, while art3 and trapezoidal approximate to the 3rd and 2nd terms, respectively.

The art3hd discretization methods a highly-stable method with good precision, especially in highly non-linear networks like the demo example provides with SPS called power_surgnetwork. mdl. The art3hd method is the only integration method capable of simulating the power_surgnetwork.mdl model with a time step greater than 90us.

SSN solver

Type of solver used for the SSN method. The SSN algorithm solves a model as two parts: state-space groups connected in a nodal method. The state-space groups can be solved by state-space discretization similar to standard ARTEMiS (art5 solver, an order 5 matrix exponential approximant) while the nodal part can be solved by Trapezoidal, Backward Euler or Balanced-zero-hold, a mix of Backward and Forward Euler. The default method is Trapezoidal. Other methods are provided for help only. In the case of numerical oscillations at nodal connection points, the Art5 or Backward Euler method can provide a solution.

Disable SSN group iterations

SSN iterates the solution within each group normally. For example, if 2 IGBTs are in the same SSN groups, iterations are made to find the correct and coherent switch pattern at all time steps. This does not apply if the switch is in different SSN groups. This option disables the internal group iteration process. This can accelerate simulations in rare cases.

Enable SSN quasi-impulse switch event check

This is an option in the SSN group iteration that should be left OFF normally. In rare case, it may improve the simulation accuracy. If a model simulation accuracy improves with this option ON, the user should consider using iSWITCH iterative models

SSN Groups maximum number of iterations

This set a limit on the number of iteration within each SSN groups. See Disable SSN group iterations option.

Maximum number of iterations (iMOV and iSWITCH)

This option controls the number of global SSN iteration when iMOV and iSWITCH models are detected inside an SSN model. This option only applies to iMOV and iSWITCH models. See Iterative Model in SSN section for more details.

Enable SSN node type verification

(new in ARTEMiS 7.1.0): Enable some verification routines related to SSN NIB type (V-type, I-type and in some case X-type). The underlying method first considers capacitors as short-circuits and inductors are open-circuits.

Basic rules are then derived:

• V-type NIB should not have a low impedance path to ground.

• I-type NIB should not see a high impedance.

• Various sets of heuristics are used when NIB paths are not clearly inductive or capacitive in nature. During I-type checking, any impedance higher than 1 e3 Ohms is considered an open circuit, while during V-type verification, any impedance lower than 0.1 Ohms is considered a short-circuit. See SSN flag option to modify these values.

The recommendation produced when this option is enabled should be followed unless it causes simulation accuracy to decrease. In the latter case, the user should contact Opal-RT support.

Use LDLT nodal admittance matrix factorization

(new in ARTEMiS 7.2.0): the SSN solver now offers a new, faster LDL^T factorization for the admittance matrix factorization. Setting this option ON will force SSN to use this new factorization. In some cases, LU factorization may be required, in the case where the global admittance matrix is not symmetric. SSN Synchronous machines, DFIM and PMSM can produce unsymmetrical admittance matrices if their speed term is included directly in the state matrix (as opposed to delayed injection).

Impulse Event Detection

This type of interpolation occurs when a forced switch action instantaneously induces a limit condition on another natural switch like a diode. A good example of this is in buck converter where the opening of a IGBT instantaneously put the free wheeling diode in conduction. This type of event is now supported by default in ARTEMiS v6 and later.

Inlined Thyristor Valves Compensation (ITVC, ITVC-SSN)

This algorithm corrects the firing jitter of thyristor valves caused by fixed step sampling of the gate signals. It automatically activates if the gate signal is a double number ranging continuously from 0 to 1. The number (ex: 0.458) indicates the in-step delay since the last sample time. The method deactivates if the number is the usual binary number used to control switches. The method is implemented in both state-space and SSN algorithms. It is used with standard Thyristor block of SPS.

Inlined Voltage Inverter Compensation (IVIC-SSN)

Available in SSN only, the IVIC-SSN method will compensate the simulation of voltage inverter modeled with SPS Universal Bridge blocks. It automatically activates if the gate signal is a double number ranging continuously from 0 to 1. The number indicates the in-step delay since the last sample time. The method naturally accounts for all working modes of the inverter, including high impedance case. The IVIC method can only be used with a special inverter model available in the SSN library.

Other types of interpolation

Custom interpolation methods are proposed in some SSN demos. See the demo ThreeLevelInverter_IVIC_RTE2.mdl for example of a 3-level NPC inverter model.

N/A

Yes

Yes

Yes