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# SSN TSB-RD (3-level Flying Capacitor)

# Library

ARTEMiS/SSN/TSB-RD

# Blocks

# Description

The TSB-RD 3-level Flying Capacitor model implements, as the name says, a 3-level flying capacitor inverter with dead-time support.

This inverter model is part of a new generation of Time-Stamped Bridge (TSB) called TSB-RD, RD standing for Real Diodes. These TSB supports interpolation methods of the previous generation of TSB. The high-impedance mode and rectifying mode are now implemented with a real SPS diode or a combination of SPS switch and thyristors (which are enablable diode in fact). Compared with the previous generation of TSB which implemented high-impedance mode with a zero-current feedback loop, TSB-RD is generally more stable and works with RC snubber of high impedance than the previous generation of TSB.

**Dead-time support**

Like the previous generation of TSB, TSB-RD blocks supports dead-time smaller than simulation time step (as opposed to SPS inverter models).

**TSB-RD recommended usage with SSN**

The TSB-RD are built using real SPS switches, diode and/or thyristor. All 3-phase inverters have 3 internal SPS switches per leg and 9 switches for a 3-phase inverter therefore, which is close to the typical limit for pre-calculation methods in real-time systems. The TSB-RD inverters are therefore best used in conjunction with SSN and put each inverter in a unique SSN group.

Three-phase 3-level Flying Capacitor circuit inverter configuration

# Mask

# Parameters

**Switch resistance (Ohms):** the internal switch (main IGBT/GTO/MOSFET and anti-parallel diode) conduction resistance in Ohms.

**Snubber resistance (ohms): **the snubber resistance in ohms.

**Snubber Capacitance (F):** the snubber capacitance in Farads.

*Note: the snubbers are always ‘in circuit’ as they are modeled by SPS components, unlike the previous generation of TSB where snubber was in-circuit only during high-impedance mode.*

**Flying Capacitance (F):** the inverter flying capacitance in Farads.

**Flying Capacitance initial voltage (V):** the inverter flying capacitance initial voltage in Volts.

**Sample Time (s):** the block sample time in seconds. Used to integrate the flying capacitor voltage.

# Input and Output signals

**Simulink connection points**

** g**: the IGBT/GTO/MOSFET gate input signals. The order of the gate signal for phase A is indicated in Figure 1. Phase B and C are following. The gate signals are Mean-Active-Duty (MAD) type with a value between 0 and 1 inclusively.

Example: a transition sequence of [ 1, 0.3, 0] means [gate ON, gate turned-on at 30% of the time-step, gate OFF])

Example: a transition sequence of [ 0, 0.3, 1] means [gate OFF, gate turned-on at 70% of the time-step, gate ON]), i.e. the MAD value depends on the transition type and is equal to the average ON time of the gate signal during the time step.

**Iabc**: the inverter output currents in Ampere.

**Vcap**: the flying capacitor voltages.

**Physical Modeling connection points**

**A,B,C**: inverter outputs for phases A,B and C.

**V+, Vn, V-**: DC-bus connection points. (**Vn** is the neutral connection point, only used as a reference point in the model)

# Examples

The demo model TSB_RD_3levelFlyCap_Drive.slx is available in the ARTEMiS path. The demo model implements a simple 3-phase inverter with the TSB-RD Flying Capacitor inverter with basic flying capacitor voltage control.

# See also

SSN TSB-RD (2-level, 3-level NPC, 3-level T-type) Help page.

# References

C. Dufour, J. Mahseredjian , J. Bélanger, “A Combined State-Space Nodal Method for the Simulation of Power System Transients”, IEEE Transactions on Power Delivery, Vol. 26, no. 2, April 2011 (ISSN 0885-8977), pp. 928-935

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