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OpDilInterface
Note : The model needs to be updated (edited on Matlab or full compilation on RT-LAB) after any modification of the I/O interface via RT-LAB, otherwise the configuration json file will not be updated within the simulation.
Library
rtlab
Block
The OpDilInterface block is used in a subsystem to create the connection between the current model and an I/O configured through RT-LAB by using the "I/O Interfaces". It handles inputs and outputs as buses, allowing easy selection of particular signals in simulations dealing with a huge number of signals.
Mask
Description
This block allows the connection of an I/O to a model by using the internal connections mechanism of RT-LAB.
It uses the I/O configuration json file generated by RT-LAB when creating a new I/O interface in the project. This file can be found at the following path: '<project_path>/configurations/SyncExchangerRegistry/DriverConfigs/'.
From a user's point of view, we simply add a block to a model.
This block takes a bus as an input and generates a bus as an output. Expected data in both buses needs to match the data described in the I/O configuration json file.
As such, outputs from the I/O become the inputs to the model, and conversely, outputs from the model become inputs to the I/O.
Workflow:
1) Add the I/O desired through the "I/O interfaces" in RT-LAB. Configure and save it. Now the configuration file for the I/O is generated in the path: '<project_path>/configurations/SyncExchangerRegistry/DriverConfigs/'.
2) Edit your model and add an "OpDilInterface" block. Double click on it to display the mask. Click on the 'Select' button to select the configuration json file corresponding to your I/O and validate.
3) Press Ctrl+D in your Simulink model to update the content of the block based on the I/O configuration json file.
4) Use the buseditor tool in Simulink to see the bus expected at the input or output of the block.
IMPORTANT : the structure expected in input must be respected (order and type of signals inside the bus)
Parameters
I/O Configuration file | Specify the path of the file containing the I/O configuration, generated busing the 'I/O interfaces' of RT-LAB Configurations are generated in <project_path>/configurations/SyncExchangerRegistry/DriverConfigs/*.json |
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Inputs
The input of this block corresponds to the bus element containing the data expected at the input of the I/O Interface. This is listed in the items of the tag 'bus_in' defined in the I/O configuration json file.
A correctly formatted bus can be easily created with the help of the Simulink block 'Bus Assignment'. While using this last block, you need to connect its first input to a constant block configured to output the expected bus format.
Note: Don't forget to compile the Simulink model (Ctrl+D) at least once before trying to connect any bus to its input
Figure 4: DIB input connection - Bus assignment configuration - Setting the input constant
Figure 5: DIB input connection - Bus assignment configuration - Selecting bus element
Important note about Bus Creator:
In the case you would want to substitute the "Bus Assignment" block with a "Bus Creator" (or cascade of "Bus Creator" to match the data structure expected by your "OpDilInterface" block), you need to make sure that the output data type of this "Bus Creator" block is set to "Inherit: auto".
Figure 6: BusCreator configuration - Output data type setup - Inherit: auto
Outputs
The output of this block corresponds to the bus element containing the data expected at the output of the I/O Interface. This is listed in the items of the tag 'bus_out' defined in the I/O configuration json file. It can be gathered with the help of a 'Bus Selector' bloc in Simulink.
Note: Don't forget to compile the Simulink model (Ctrl+D) at least once before trying to access any bus from its output
Figure 7: DIB output connection - Bus selector configuration - Selecting bus element
Characteristics and Limitations
This block has no special characteristics.
Direct Feedthrough | Yes |
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Discrete sample time | Yes |
XHP support | Yes |
Work offline | No |
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