HYPERSIM Release Notes: 2019.1

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HYPERSIM Release Notes: 2019.1


HYPERSIM

Added

  • Added new Renewable Energy example models for PVGS, FCGS, BESS and CHP

  • Added support for MATLAB R2018a and R2018b

  • Added data logger capability to start and stop recording while the simulation is running

  • Added dynamic file management capability to the data logger

  • Added load flow support to UCM

  • Added autotransformer model

  • Added transceiver models for voltage and current signals

  • Added point of current measurement in thyristor model

  • Added an option in the ribbon to export the design in EDD format

  • Added support for I/O factor with new UI-based I/O system in the sensor view

  • UI: Added capability to draw diagonal signal lines

  • UI: Added capability to connect a bundle input to multiple outputs

Improved

  • Improved default performance factor value to 20

  • Improved workflow of the content editor with an expression analyzer

  • Improved workflow with snapshot by providing it directly in the main HYPERSIM ribbon

  • Improved workflow and fixed various issues with the Target Manager

Fixed

  • Fixed Advanced target settings that were not applied before simulation or saved with the model

  • Fixed missing iteration parameter in "3-winding, w/ sat + tap + dec" transformer

  • Fixed API function setSensorDataPoint()

  • Fixed PT block error when using it as a network element mode

  • Fixed transformers not displayed in Base Voltage view of the netlist if neutral pin is visible

  • Fixed gcc compilation command not working

  • Fixed issue with 1-phase wideband line model

  • Fixed default value for the task mapping performance factor being too low

  • Fixed issue with driver configuration update progress bar persisting after the update is completed

  • Fixed various issues with non-persisting preferences

  • Fixed issue with lost data when changing the number of points on a saturation curve

  • Fixed wideband fitter failing to generate data

  • Fixed issue with simulation preferences being saved on Apply instead of with the model

  • Fixed R-L coupled wrong pin type that should be 3-phase only

  • Fixed network issue that could cause a time out during code generation

  • Fixed 1-phase to 3-phase connection type change not taken into account at the next Analyze

  • Fixed issue with .pun file not loading in the DC line model

  • UI: Fixed various bundle and breakout connection issues

  • UI: Fixed Advanced Find window not hiding and re-showing correctly

  • UI: Fixed various issues in Edit Symbol mode

  • UI: Fixed various issues in Library Maintenance

  • UI: Fixed rename issue after copy/paste action

  • UI: Fixed issues with Observables on subcircuits

  • UI: Fixed Parts Library disappearing when floated

I/O Interfaces

C37.118 Master

  • Added "Mismatch" connection point providing information whether the master has a different number of data configured
    than the slave

DNP3 Master

  • Added option to execute the driver on a dedicated core

  • Improved data mapping using editable custom names instead of preconfigured order

DNP3 Slave

  • Added option to execute the driver on a dedicated core

IEC 61850

  • Fixed GOOSE messages corruption when daName refers directly to a basic
    data attribute

  • Fixed cVal.mag.f data attribute parsing

Modbus Slave

  • Added option to configure the initial values

OPAL-RT Boards

  • Added support for Multi-System Expansion link (MuSE)

  • Added support for new Artix-7 FPGA board (OP5143)

OPC-UA

  • Added support for OPAL-RTLinux 64-bit



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