HYPERSIM

Added

• Added the possibility of having negative initial flux in 2-Winding 1-Phase Saturable Transformer 

• Added the following Python API | Commands:

  • recheckPorts 

  • setDeviceFillColor 

  • setDeviceLineColor 

  • setSignalLineColor 

  • setSignalLineWidth

  • setProperty

  • option name in the addDevice command 

• Added output integrator (1/sTe) to have non-windup limits on AC8B exciter library model 

• Added support for OP4510 in FPGA-Based PMSM Drive Transportation example model 

• Added the possibility in the Task Manager view to copy lines of the "prodID" column to the "set procID" column  

• Added diode in PV Array model to remove operating temperature limitation 

• Added capability to bulk edit the execution time estimate of multiple tasks in Task Manager 

• Added Warning message when clicking on Clear sensor 

Improved

• Improved the Signal Monitoring component by allowing it to be displayed as an LED

• Improved value accuracy displayed by the Signal Monitoring block:  

• Improved error message when the target license expires 

Fixed

• Fixed phase A voltage mismatch when switching between balanced and unbalanced modes in voltage source 

• Fixed I/O factor column not showing when selecting "I/O" view in sensor summary 

• Fixed issue when setting to 0 the lower limit of the PID integral integrator of AC8B exciter model during a voltage reference decrement test 

• Fixed unapplied limitation on number of taps (50) in transformers 

• Fixed DNP3 Slave configuration in DNP3_MASTER_SLAVE example model 

• Fixed issue with Python API setCommandParameter when the parameter is of type String 

• Fixed wrong user feedback indicating clearing of previous load flow information when clicking on Set Initial Conditions 

• Fixed crash when putting wrong number in I/O connection column of sensor menu 

• Fixed pu option not available in forms of Switches and Breakers components 

• Fixed display issue where some menus show a white page when using remote desktop connection 

Removed

• Removed internal ground in the PV Array model

I/O Interfaces

General

• Improved view for OPAL-RT Board and C37.118 master I/O interfaces 

• Fixed driver setup and cleanup commands not properly being registered when using multiple models during the same HYPERSIM session 

OPAL-RT Board

• Added support for OP5330 analog out cards with configurable sampling rates 

• Added support for the OP5143 Artix-7 board enabling I/O expansion through fiber optics on the OP5033XG platform 

• Added debugging feature to log register accesses during simulation load 

• Fixed isolation losses on OPAL-RTLinux 3 (x64-based platform) 

FPGA-Based Simulation

A more detailed list of release notes is available at C:\OPAL-RT\eFPGASIM\v2.8.2\Docs\ReleaseNotes

• Added initial (beta) release of eHS Gen5 core, enabling faster simulation and PWM frequency resolution up to 250 kHz

• Added support for up to 8 Time-Stamped Bridge (TSB) in eHS Gen5 (EFS-4571, EFS-4560)

• Added new OP4510 firmware with support for 2 machines and the following I/O configuration: OP5369, OP5330-3, OP5342 and OP5330-3 (EFS-4367)

• Added support for Roff in Gen 4 Half-Bridge parser to improve stability (EFS-4386)

• Added error for exceeding the maximum number of supported AC sources (EFSTT-1103)

• Improved eHS and machine drivers to enhance the numerical stability of simulations

• Fixed FPGA reset issue with Generic machine model (EFS-3999)

• Fixed eHS circuit loading failure while modifying circuit without closing the FPGA-based circuit component form between attempts (EFSTT-1104)

• Fixed issue with Sources having the same name (in Schematic editor subsystems) appearing as a single interface port (EFSTT-1095)

Communication Network Simulation

• Added a new I/O interface to facilitate configuration of EXata CPS on OPAL-RTLinux 3 (x64-based platform)