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Table of Contents

Description

FPGA-Based Circuit

This component allows creating, editing, configuring and running an FPGA-based circuit. It provides access to the OPAL-RT Schematic Editor specifically designed to develop circuits for FPGA-based simulation. Multiple parameter sets can also be predefined to enable switching test cases while the simulation is running.

It is dedicated to the S-function driver which allows a smooth migration from Simscape Electrical Specialized Power Systems (SPS) workflow to Schematic Editor Workflow.

Workflow

First usage of the block will open the mask. Any further usage will open directly the Schematic Editor with the selected circuit.

In order to fine tune configuration, a context menu (Right Click > eHS Block) enables advanced feature:

• Circuit selection and driver settings

  • Opens the mask

• Update block

  • Update the block after a circuit change

• Open build report

  • Opens the eHS build report of the latest update

• Advanced Features Menu

  • Features for advanced users (further information in the section below)

Update diagram action will also trigger the update block and return associated errors if any.

Mask Parameters

Name: Dropdown menu to select the circuit to be simulated from the user database.

Refresh: This action updates the dropdown list of circuits available from the user database.

Edit: This action opens the selected circuit in the Schematic Editor.

Create new: This action creates a new circuit in the Schematic Editor.

Load circuit: This action loads the selected circuit into the Simulink block. The block is automatically redrawn, I/O and FPGA configuration files are updated.

Open Logs: This action opens log folder in the windows browser.

Open Build Report: This opens the the latest eHS Build Report in your preferred text editor.

Controller Name: This field will allow the block to synchronize with the S-Function driver. It must match the OpCtrl block name. (Only available in S-Function driver)

Auto configure OpCtrl/OpLnk Block: This checkbox will automatically set the OpCtrl's Primary Bit File Name to the firmware information in the Schematic Editor's simulator setup. (Only available in S-Function driver)

Inputs, Outputs and signal available for monitoring

Inputs

Controlled sources inputs: Drive the controlled current and controlled voltage sources of the Schematic Editor circuit.

Switches inputs: Control the switches of the Schematic Editor circuit.

Parameter set id: Only available if additional parameter sets are defined in the Schematic Editor. Allows the user to change the parameter set applied during the real time simulation.

Reset: Only available if the "Reset Pin" option in "Solver Settings" in the Schematic Editor is set to "On". Allows the user to reset the eHS outputs and machine outputs to 0.

Outputs

Dynamically generated: The outputs represent real time measurement values that were placed into the Schematic Editor circuit.
Note that eHS voltage and current measurements are averaged over a CPU model time step (a moving average function is performed on the FPGA device).
Exception: the measurements coming from machine blocks that are zero-hold sampled.

Parameter Set

Parameter set allows changing multiple circuit's component parameters during the simulation without having to reflash the firmware or stop and restart the simulation. Parameter sets' values, names and IDs can be defined in the Schematic Editor while editing the circuit.

Advanced Features Menu

A sub menu "Advanced Features" is available when right-clicking on an eHS SE Driver block in the menu "eHS Block".

It brings the functionalities explained right below.

Switch eHS SE SFunction Drivers / Switch to eHS SE OpalBoards Drivers

A right click option is available to switch between the two supported eHS SE Drivers, S-Function and OpalBoards.

It allows to replace the current driver without the need to reconnect the block's inputs and outputs in Simulink. It automatically reloads the Schematic Editor circuit if a circuit was loaded.

Export to protected model

This feature creates a new compiled Protected Block containing all the configuration information for the selected circuit without granting the Protected Block's user access to the circuit or its parameters.

Upon exporting the original block to a Protected Block, the circuit will be loaded based on all the defined Simulator Setups inside the Schematic Editor. All the resulting configuration files, at the moment of exportation, will be saved inside the new Protected Block.

The resulting Protected Block has the same behavior as the original one, except the ability to access or make modifications to the circuit. It is not required to have the OPAL-RT Schematic Editor installed in order to use a protected block to run a RT-LAB online simulation. The simulation will be run with the files and configuration that was generated at the moment the block was exported. This gives the circuit designer and integrator the ability to hide sensible information of the circuit to a user while still granting the ability to run said circuit on a RT-LAB online simulation.

Since the details of the circuit are accessible with the OPAL-RT Schematic Editor, the I/O configuration for each setup along with additional information may be consulted in "Build Report Tab".

Troubleshooting

If you see the message "OPAL-RT Unified Database is unavailable" beside the "Load circuit" button, verify your installation of the OPAL-RT Unified Database. If after clicking on either the "Edit" or "Create" button and the message "OPAL-RT Schematic Editor is unavailable" is displayed, verify your installation of the OPAL-RT Schematic Editor.

After clicking the "Load circuit" button, the configuration and binary files are automatically generated and placed in a folder called OpalBoardsAddons beside the model. You do not need to copy such folder when moving the project to another place.

In the case where loading a circuit succeeds, the 'Open Build Report' link will open a detailed eHS Build Report that contains advanced circuit information such as effective and minimum achievable time-step and all eHS input and generated outputs.

In the case where loading a circuit fails, a notification message appears. Please refer to our User Notifications from FPGA Power Electronic Toolboxfor more details.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.