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This example model can be found in the software MMC under the directory of /Examples/MMC_cpu_STATCOM

Description

This demo simulates the MMC STATCOM model. It has the capability to simulate in the CPU model or in the AVM model upon the selection of users. With the CPU mode, the detailed MMC valve will be simulated; While with the AVM mode, the averaged MMC valve will be simulated. Users can change the mode from one to another during the time of simulation. The model operation mode is configured in MMC CPU Parameter block.

This demo system of the full bridge MMC STATCOM is modeled using optimized RT-Lab MMC block, which can be used for half-bridge, full-bridge, clamp-double and T-type MMC cells. The demo shows the model can simulate either off-line with much faster simulation speed comparing to other offline simulation software, or in real-time. A full-bridge MMC cell consists of a dc capacitor, a discharge resistor, and four power electronic switches.

Each switch includes an IGBT, an anti-parallel diode. The MMC block models up to maximum 50 individual MMC cells. Multiple MMC blocks can be piled up to model an MMC valve of more than 50 cells. The MMC block has following features:

• The values of cell capacitances and the discharge resistance can be adjusted during simulation.

• There is a dead-time between each pair of upper and lower gates.

• Temporary or permanent short circuit of cell capacitor in any cells can be simulated.

• There are normal mode and debugging mode. In the debugging mode, the capacitor voltages can be set to average value (to temporarily replace voltage balance control)or a fixed value.

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Please refer to the help file of MMC CPU Parameter block for more information of setting relevant parameters.

The STATCOM model is composed of MMC CPU Model Configuration block and VSC Node block, please refer to the help file for more information of setting relevant parameters. The VSC Node block is used to represent the behavior of a valve circuit based on the calculations from MMC CPU Model Configuration block.

The signal interactions between the valve and the calculation block are done internally. Notices the number of VSC Node block presented in the circuit has to match the setting in the MMC CPU Model Configuration block. In this demo, only 3 valves are presented in the model following the structure of MMC STATCOM.

Circuit Description

The MMC STATCOM is studied in a test system as in the figures below. The test system parameters are given in TABLE I. There is 100 MVA load at the bus of point of common coupling (PCC) with a power factor of 0.95. The short circuit ratio (SCR) at PCC is approximately 4, which means the STATCOM has a weak connection to the grid. The STATCOM parameter is given in TABLE II. The carrier signal has a low frequency, i.e. 5 times the line frequency. The arm inductor has a value of 0.1 p.u.

Simulation and Results

Various phenomena can be studied using the MMC model. In this demo model, four scenarios, i.e., the steady state, voltage sag, 3-phase-ground ac fault, and SM capacitor dc fault, can be studied and the results are presented in the reference paper [1]. The model can be controlled and simulation results can be monitored during simulation in the console subsystem.

For the control:

• para is to set the MMC parameters.

• load shed is to connect to (=1) or shed (=0) the load.

• ac no_fault is to set a 0.05sec (adjustable in the model) 3-phase-ground fault at PCC.

• voltage sag is to set voltage sag at source bus (0 for no sag, and 0.1 for 0.1 pu voltage sag).

• ctrl mode set the STATCOM either in voltage mode or Q mode. The voltage mode controls the voltage at PCC to 1 p.u. as long as reactive power allows. The Q mode control the reactive power to the set value set at the q_ref.

Note: after starting the simulation, the "Enable pulse" checkbox inside the MMC (CPU) parameters block should be checked in order to enable the STATCOM's operation.

For the monitoring:

The first scope "measscope1" displays respectively from the topmost to the lowermost sub-scopes:

1. 4 signals, i.e. STATCOM voltages in phases a, b, c, and neutral.

2. 4 signals, i.e. the maximum, minimum, average of all capacitor voltage and the value of the 1st cell.

3. 3 signals, i.e. average capacitor voltage of phases a, b, and c.

4. 3 signals, i.e. source bus voltages in phases a, b, and c.

5. 3 phase voltages.

6. 3 phase currents.

7. 3-phase active and reactive powers.

Real-time Performance

The model has been run on a dual-Xeon based 3.466 GHz CPU with Red-hat operating system. The time-step is 20 µs, and 1 CPU core have been assigned. Note the time step is as short as 20 µs. The model can run in 2 modes, the CPU mode and the AVM mode. The real-time simulation performance will be different with the 2 modes.

With both converter running under the CPU mode, the performance is shown as following:

With both converter running under the AVM mode, the performance is shown as following:

References

[1] Wei Li, L.-A. Gregoire, and Jean Belanger, "Modeling and Control of a Full-Bridge Modular Multilevel STATCOM," IEEE Power and Energy Society General Meeting, 2012, 7 pages.

See Also

 MMC CPU Parameter block, MMC CPU Model Configuration block, VSC Node block