HYPERSIM

Added

• Added exciter library model:
  • REXSYS
• Added governor library model:
  • WESGOV
• Added example models :
  • Static Synchronous Series Compensator (SSSC)
  • Unified Power Flow Control (UPFC)
  • Kundur 4-Machine Power System
  • IEC 61850 Substation Automation System (SAS)
• Added support for Python version 3.7 
• Added the following Python API commands:
  • getAllDevicesNames 
  • renameSignal 
  • addPinsToDevice
  • createSubCircuit
  • ScopeView.setDataSourceParameter
• Added subcircuit support in the following Python API commands:
  • addDevice
  • includeDevice
  • removeDevice
  • renameDevice
  • connectDevices
• Added Signal Routing library models allowing sending/receiving signals through all levels of subcircuits or pages without the need for drawn wires
  • Radiolink emitter
  • Radiolink receiver
• Added Multi-Breaker and CmdLine commands in TestView
• Added error message to prevent users from opening more than one instance of HYPERSIM
• Added option to "solve control inputs before solving power" advanced option in simulation settings. It remains unchecked for existing examples but is activated by default with newly created models.
• Added support for EXST1 and ST1A in PSS®E import
• Added carrier frequency input and dead time parameter in PWM average generators for 2-Level Converter and Full-Bridge Converter

Improved

• Improved I/O assignment and sensor management workflow 

Fixed

• Fixed issue where some signals in a bundle would be renamed during EDD import, potentially leading to wrong signal connections on the same observable 
• Fixed issue where some signal names could conflict during EDD import, potentially leading to import interruption by a popup 
• Fixed the output behavior of H(s) component at the beginning of the simulation when a non-zero constant is connected to the "init" input or a zero constant is applied at input "u" 
• Fixed DC Circuit Breaker form default values to avoid solver divergence in some cases 
• Fixed Task Manager's SaveConfig option wrongly opening OpenConfig menu 
• Fixed issues with scripts generated using a template in the Sequence Manager where paths include space characters
• Fixed issues with EDD import when models containing UCMs have their .def file located next to the .edd file
• Fixed Control Exciter library models:
  • AC2A: Fixed the initialization of VA0 and the non-windup integrator producing the VE signal
  • EXAC3: Fixed Efd output at the initialization of the feedback loop signal when EFDN > Efd0
  • EXST1: Fixed various issues with In1, Vt and Vc1 pins and the lower limit of the exciter
• Fixed Autotransformer displayed base winding voltages in rmsLL

• Fixed Voltage Source base voltage value in EDD export

• Fixed several components that were not reported under the correct category in the Netlist
• UI: Fixed issue where some connections wouldn't show on the design when connecting multiple pins to the same bundle
• UI: Fixed default signal names being cleared when doing Paste Special with "keep old names"
• UI: Fixed new default names occasionally assigned to devices on Paste Special even if "keep names" specified

Removed

• Removed protection example model:
  • Distance 21 POTT.

I/O Interfaces

General

• Improved network configuration through harmonization of parameters across relevant interfaces (C37.118, DNP3, IEC 60870-5-104, Modbus) and implementation of automatic IP aliasing generation

C37.118 Slave

• Fixed driver behavior when multiple points connected to the same sensor

DNP3

• Added support for double bit binary input
• Added support for integrity polling (new read mode)
• Added support to run the driver on Windows

IEC 60870-5-104

• Fixed display issue in point lists of the configuration menu

IEC 61850

• Fixed model loading and resetting issues coming from an incompatibility between IEC 61850 and Modbus RTU (Master and Slave)

Modbus Slave/Master

• Fixed initialization failures due to synchronization issues

OPAL-RT Board

• Added support for OP5369 digital card

Synchronization

• Added automatic discovery of the network interface name

FPGA-Based Simulation

• Added support for user-defined time step configuration
• Added generation of eHS compilation logs
• Added support of OP4510 Kintex-7 410T based firmware
• Added support for QE on RS422
• Added support for configuring more than 32 AO channels
• Improved the names of machine input and output signals
• Fixed issues with configurations using more than 2 SCIM/DFIM/SM
• Fixed the output amplitude of DQ voltage of the SCIM/DFIM/SM being dependent on time step

Communication Network Simulation

• Improved user workflow (DRV-3736)