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V2.20 Kintex-7 410T - eHS x128 - Gen5 - PMSM - IO Config2
- Fabien Ducat
OPAL-RT TECHNOLOGIES
1751 Richardson suite 1060, Montréal QC Canada H3K 1G6
www.opal-rt.com
© 2023 OPAL-RT TECHNOLOGIES All rights reserved
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SCHEMATIC EDITOR WORKFLOWSCHEMATIC EDITOR WORKFLOW WITH SFUNCTION
Introduction
This firmware includes:
One eHS x128 Gen5 Solver
- One Dual Permanent Magnet Synchronous Machines (PMSM-VDQ) model
One Analog Output Mapping and Rescaling (AOMR) module
One Analog Input Differential Rescaling (AIR) module
One Thermal Losses (TL) module
One Saturable Transformer (satXFO) module
LoadIn/DataIn/DataOut mapping
LoadIn | DataIn | DataOut | |
1 | Config eHS | Inputs eHS | eHS Averaged |
2 | Scenario / Rst eHS = Status | TSDO 1 - eHS 0 to 7 | eHS DownSample |
3 | TSDO 2 - eHS 8 to 15 | Digital In 1A - 0 to 7 | |
4 | PWM 1A - 0 to 7 | TSDO 3 - eHS 16 to 23 | Digital In 1A - 8 to 15 |
5 | PWM 1A - 8 to 15 | TSDO 4 - eHS 24 to 31 | Digital In 1A - 16 to 23 |
6 | PWM 1A - 16 to 23 | TSDO 5 - eHS 32 to 39 | Digital In 1A - 24 to 31 |
7 | PWM 1A - 24 to 31 | TSDO 6 - eHS 40 to 47 | Analog In 2A - 0 to 7 |
8 | TSDO 7 - eHS 48 to 55 | Analog In 2A - 8 to 15 | |
9 | TSDO 8 - eHS 56 to 63 | eHS Period Averaged | |
10 | TSDO 9 - eHS 64 to 71 | eHS Period DownSample | |
11 | Digital Out 1A - SDO 0 to 7 | TimeOn Averaged | |
12 | Config AOMR | Digital Out 1A - SDO 8 to 15 | TimeOn DownSample |
13 | eHS PWM 1 - eHS 24 to 31 | Digital Out 1A - SDO 16 to 23 | Thermal Losses |
14 | eHS PWM 2 - eHS 0 to 7 | Digital Out 1A - SDO 24 to 31 | RMS and Power calculation |
15 | eHS PWM 3 - eHS 8 to 15 | PMSM VDQ 1 | |
16 | eHS PWM 4 - eHS 16 to 23 | ||
17 | Config eHS AIR | ||
18 | Config PMSM VDQ 1 | ||
19 | AOMR/ Analog Out 1B - 0 to 7 | ||
20 | Analog Out 1B - 8 to 15 | ||
21 | Config Thermal Losses | Analog Out 2B - 0 to 7 | |
22 | SFP | Analog Out 2B - 8 to 15 | |
23 | Lookup Table Config | eHS PWM 1 - 0 to 7 | |
24 | RMS and Power calculation | eHS PWM 2 - 8 to 15 | |
25 | eHS PWM 3 - 16 to 23 | ||
26 | eHS PWM 4 - 24 to 31 | ||
27 | eHS SWG | ||
28 | PMSM VDQ 1 | ||
29 | |||
30 | |||
31 | |||
32 | |||
33 | Thermal Losses | ||
34 | SFP | ||
| 35 | |||
| 36 | Lookup Table Config |
System Overview
Extensive I/O compatibility (Polymorphism)
Listed cards are compatible at the same location
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Permanent Magnet Synchronous Machine models (PMSM VDQ)
A total of two PMSM motors are available and configured using the Permanent Magent Synchronous Machine. The machine type could be Constant DQ, Variable DQ or BLDC.
Schematic Editor Workflow - PMSM (VDQ - BLDC) block
Communication port configuration for the Dual PMSM (VDQ) block
| Dual PMSM Motors VDQ | |
Machine Label | PMSM 1 | PMSM 2 |
Data In Port Number | 28 | |
Load In Port Number | 18 | |
Data Out Port Number | 15 | |
Connectivity (Input)
Analog In - Slot 2A - Ch00-15
Encoder Output
Digital Out - Slot 1A - RS422
| Encoder 1 | Encoder 2 | |
|---|---|---|
| A | Ch00 | Ch04 |
| B | Ch01 | Ch05 |
| Z | Ch02 | Ch06 |
SFP Mapping and Communication Block
A total of 32 inputs and 32 outputs are available and configured using the SFP mapping and communication block.
Schematic Editor Workflow - SFP Mapping and Communication block
Communication port configuration for the SFP mapping and communication block
SFP - Channel 0 | |
|---|---|
Data In Port Number | 34 |
Load In Port Number | 22 |
Analog In module (AI)
AI block reads signals from analog input channels on the simulator.
Schematic Editor Workflow - OPAL-Board/AI
RT-LAB
HYPERSIM
Power calculation module
SPS WORKFLOW SPECIFIC SCHEMATIC EDITOR WORKFLOW WITH SFUNCTION
RMS and power calculation for all circuit measurements is configured using the “Power Measurement Controller” block in the CPU model.
For more documentation on the block see : https://opal-rt.atlassian.net/wiki/spaces/PFPET/pages/65835684/CPU+Power+Measurement+Configuration+-+efs+Monitoring+cpuPowerBlock
Communication port configuration for the Power calculation block
RMS | |
|---|---|
Load In Port Number | 24 |
Data Out Port Number | 14 |
Analog Out module (AO)
AO block configures analog output channels on the simulator.
Schematic Editor Workflow - OPAL-Board/AO
RT-LAB
HYPERSIM
Digital In module (DI)
DI block reads signals from digital input channels on the simulator. It could be static, TSDI or PWMIn.
Schematic Editor Workflow - OPAL-Board/DI
RT-LAB
HYPERSIM
Digital Out module (DO)
DO block configures digital output channels on the simulator. It could be static, TSDO or PWMOut.
Schematic Editor Workflow - OPAL-Board/DO
RT-LAB
HYPERSIM
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