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Switched Reluctance Motor Hysteresis Controller - efs_cpuSrmHysteresisController

Block


Table of Contents

Description

This block is used to initialize, monitor and control on FPGA SRM controller.


Mask Parameters

Controller Name: Links this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block. The OpCtrl block controls initialization of the settings of one specific FPGA-based card in the system.

Controller Settings (SRM Type) : This should specify the SRM type useed in the model.

Load In Port Number: This should reflect the LoadIn port used to configure the SRM Hysteresis Controller in the FPGA.

Data Out Port Number: This should reflect the DataOut port used to receive the SRM Hysteresis Controller data from the FPGA.


Inputs

Iref_max: This represents the upper bound of the controller reference current.

Iref_min: This represents the lower bound of the controller reference current.

Turn_on_angle: This represent the angle for switching the phase supply on.

Turn_off_angle: This represent the angle for switching the phase supply off.

Rst: Reset of the FPGA motor solver.


Outputs

Controller Out: This output returns the set up controller output.


Characteristics and limitations

Direct FeedthroughNO
Discrete sample timeYES
XHP supportYES
Work offlineN/A


If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.

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