Description

The 24-Phase Hysteresis Controller block implements the driver of the FPGA-based 24-Phase Hysteresis Controller. The settings of this parameter panel are transformed into the control signals of the FPGA-based controller.

Mask Parameters

Hysteresis Controller tab

Trapezoidal table: [min -1 max 1]: Current reference shape table that depends on the electrical angle. It must be a vector with the same number of elements as the breakpoints vector. Table values with breakpoints outside the 0-360 range will not be used.

Trapezoidal table breakpoints: [0=>360deg]: Angle breakpoints of the trapezoidal table. It must be a vector with the same number of elements as the trapezoidal table. Breakpoints outside the 0-360 range will not be used.

Square table: [min 0 max 1]: When the table values are 1, it defines when the gate 4 and 1 should be controlled, so when the controller should drive a positive current. In opposite, when the values are 0, only gates 2 and 3 are driven, so it defines when the controller should drive a negative current. Only 0 or 1 values are sent to the FPGA, other values will be rounded to 0 or 1. It must be a vector with the same number of elements as the breakpoints vector. Values with breakpoints outside the 0-360 range will not be used.

Square table breakpoints: [0=>360deg]: Angle breakpoints of the square table. It must be a vector with the same number of element as the Square table. Breakpoints outside the 0-360 range will not be used.

Theta offset: [deg] [24x1]: Angle offset of each phase. For example: 0 15 30 45 60 75 90 etc. if you have 15 degrees offset between two consecutive phase. It must be a 24-element vector.

Iratio: [24x1]: Adjutment gain of each phase measurement. It must be a 24 element vector (one by phase current). By default, it's set to ones(24,1) when no adjustments need to be done.

Default Hysteresis band: [amps]: Default value of the hysteresis band width. The hysteresis band is defined by iref + hysteresis_band and iref - hysteresis_band.

Current measurement sampling period: [sec]: Sampling period of the current measurement. The smaller this period the better the control results are. The minimum period is about 250ns. The largest period is about 30ms.

Configuration tab

Hardware Controller Name (OpCtrl): Controller Name label of the OpCtrl or OpLnk block which must be linked with this block.

FPGA Clock Period: [sec]: This parameter is locked to the FPGA clock period, which is 5ns by default.

Configuration Port Numbers: Port number of the various configuration ports used within by this block. These port numbers are specific to the FPGA firmware version. Please check the bitstream documentation to know these port numbers.

Inputs

Iref: Controller reference current. This value will set the current setpoint.

Hyst_band: Width of the hysteresis band. The hysteresis band limits are Iref + hyst_band and Iref - hyst_band.

Angle Offset: Angle shift that can be added to the controller to simulate the delay that exists in real hardware between the actual angular position of the rotor and the measurement provided by the encoder.

Force_Imot: This input port can be used to set manually the measured value of the current with the Imot input. If the input is set to 0, the measured values are taken from the motor solver. If the input is set to 1, the measured values are taken from the Imot input of the block.

Imot: This input sets the forced current measured values. It must be a vector of 24 elements (one for each phase).

Theta_forced_en: This input port is used to override the angle value read by the controller. If set to 0, the angle value used by the controller is the output of the motor solver. If set to 1, the angle value used by the controller will be the theta_forced input value.

Theta_forced: Forced angle value used when theta_forced_en is enabled (set to 1). This must be a scalar, in degrees. This angle is referred to the electrical angle.

Outputs

Gates: State of the controller output gates. There are 4 gates per phase (for a total of 96) named G1, G2, G3 and G4. Inside the FPGA, they are pre-routed to the switches Inside the FPGA, they are pre-routed to the switches 1, 2, 3 and 4 as shown in the figure below.

comm_status: Communication ports status for debug and monitoring of the FPGA/CPU communication.

Characteristics and limitations

Models that include this block should be provided with a detailed description document. Refer to this document to obtain more information about the block specifications.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.