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Table of Contents

 

Description

This block allows the configuration and the control of a eHS Gen4 solver to compute the outputs of a power-electronic circuit. The eHS Gen4 core is located on an FPGA-based board and runs at a higher sample rate than an RT-LAB system. The netlist file must be a Simscape Electrical Specialized Power Systems (SPS) Simulink model.

The block enables the real-time control of its voltage and current sources, as well as the gate signals of the switches. In addition, it supports scenario management.

Mask Parameters

Circuit Tab

eHS Solver License Class: This will define the eHS solver size applied for the real-time simulation. If the Auto mode is selected, this circuit will simulate using the eHS solver size defined inside the firmware directly. Otherwise, the user can select a smaller or equal size compared to the one specified in the firmware. The license will be checked based on this selection and thus, the performance of eHS will be limited. For license keys related to eHS, please click the following link for more information eHS Solver License keys.

Generate Configuration: By clicking this button, the circuit file will be imported and the block updated with the latest file information.

Circuit file name: This field displays the file name describing the circuit intended to be simulated using eHS. The system should be built using the Simscape Electrical Specialized Power Systems (SPS) Toolbox. See the product documentation and example models for details on how to design the circuit for use with the eHS.

[...]: Opens a file explorer window to browse the circuit file.

Edit: Opens the circuit file in Matlab.

Use Explicit Time-Step (Otherwise Use Minimum): If this option is selected, the eHS Time-Step field is displayed to set the solver sample time. The minimal solver sample time depends on the complexity of the circuit, and typically ranges in the hundreds of nanoseconds.

This may be helpful for:

• Testing different sample times

• Reducing the quantization error for systems that contain very large time constants (>> 10sec)

• Synchronizing the eHS with another FPGA solver core

Show advanced settings for eHS solver: This checkbox allows the user to modify the switch conductance and initial voltage and current values. If unchecked, the last applied configuration of these parameters will be used.

Use Explicit Gs Values (Otherwise Use 1): If this option is selected, the Switch conductances field is displayed to set conductance of the switches of the circuit. If it is a scalar, this value is applied to all switches in the circuit. If it is a vector, each element is applied to the switch with the corresponding index in the circuit to be solved. Valid values of Gs are positive or null. However, while null values are allowed, they may lead to incorrect simulation results and using them will trigger a warning display.

To open the eHS Optimization Tool in order to get more info on this parameter, type GsGui2 into the MATLAB Command Window.

Inputs Tab

Configure Inputs: This button enables the user to open the eHS input configuration panel.

eHS Input Configuration: This table allows you to connect any source of the circuit to the available sources (CPU Model, Sine Wave Generator, Analog Input). The index specifies the channel of the associated source to use.

Automatic channel assignement: If enable, this channels of "Sine Wave Generator" and "CPU Model" will be automatically assigned (in the order of the Input Name list) based on the number of connexion made to the associated source. If disable, the user can use the index of his choice in the acceptable range.

Gates tab

Configure Switch Gates: This button enables the user to open the eHS gate configuration panel.

Use RT-EVENTS: If this option is selected, the Number of Events field is displayed to configure the number of events of the internal Time Stamped digital pulse generator (by default 4).

eHS Gate Configuration: This table allows you to connect any source of the circuit to the available sources (CPU Model, Internal PWM generator, Simulator Digital Input). The index specifies the channel of the associated source to use. The polarity field is to set the gate signal polarity (High => if eHS reads a digital state of 1, the gate applied to the switch will be ON; Low => Digital state of 0 means gate applied is ON)

Scenario Management Tab

The scenario feature allows the user to define multiple sets of values for the netlist RLC components. For each scenario, the user will be able to modify the values of the components.

Use scenarios: By checking this option, the scenario feature will be enabled.

Generate a scenario file template: This button generates an empty scenario file based on the user's circuit file. This requires Microsoft Excel to be installed on the host computer in order to produce a file.

[...]: Opens a file explorer window to browse the scenario file (xls or xlsx file).

Edit: Opens the circuit file in Matlab.

XLS File name: The XLS file contains the table of RLC components values depending on the scenario number. This parameter gives the path of the file that will be used to perform the scenario declaration.

Maximum number of Scenarios: This represents the number of scenarios available for the current netlist. This number takes into account the scenario of default values that cannot be modified.

Thermal Loss Management Tab

The thermal loss feature allows the user to assign switching loss, and conducting loss for 2-levels bridge. Every 2-levels bridge can be configured using one of four lookup table defined for the switches, and their anti-parallel diode. Note that this feature does not affect the simulation results. Losses shown here are not added nor substracted from the simulation.

enable: By checking this option, the thermal loss feature will be enabled.

Configuration: This button enables the user to open the eHS Thermal losses Configuration panel.

eHS Thermal losses Configuration: This table shows every Inverter leg in detected in the circuit. The eHS will automatically populate the list of legs form the Universal bridge blocks found in the circuit model.

• The first column shows their names.

• The Enable column allows to choose which inverters leg are monitored. A maximum of 30 two-level inverters leg, or 120 devices, can be monitored during a simulation.

• The DC Voltage and AC Current columns show the measuremt used to compute the thermal losses.

• If the Automatically find measurements is checked, those two columns are filled automatically. If they are Unassigned, it indicated that they are either missing, or not connected properly. DC Voltage measurement positve point should be connected to the positive DC-side of the two-level inverter. DC Voltage measurement negative point should be connected to the negative DC-side of the two-level inverter. AC Current measurement positive point should be connected to the AC-side (A B or C node) of the two-level inverter (positive current is defined exiting the inverter).

• The thermal model column lets the user assigned one of the four lookup table.

• T° port indices column indicates where the component temperature should send on the devices T° port vector.

For more information on how to fill the different Thermal model and their Switch and Diode characteristics please use the following link for the Thermal loss documentation.

Comm Settings Tab

OpCtrl Controller name: Links this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block. The OpCtrl block controls initialization of the settings of one specific FPGA-based card in the system.

Communications Settings Automatic Configuration This will enable the automatic setting of the communications ports. The *.conf file linked to the *.bin file selected in the OpCtrl Controller will be parsed and the communications settings will be set accordingly. If unchecked, the fields become modifiable for manual user settings.

Ehs Core If Communications Settings Automatic Configuration is enabled, Ehs Core allows the selection of which core defined in the *.conf to use for automatic configuration. To know more about how cores are defined inside a *.conf file, see: Conf File Writing Conventions

eHS Form Factor This parameter shows the eHS solver size instanciated inside the firmware. It is disabled if the mode "Communications Settings Automatic Configuration" is selected, since the eHS Form Factor value will be read from the *.conf file.

Cpu Inputs Port Number: From the Communication Port Numbers array mask, this value will show the effective Cpu Inputs Port Number

Cpu Gates Port Number: From the Communication Port Numbers array mask, this value will show the effective Cpu Gates Port Number

Cpu Outputs Port Number: From the Communication Port Numbers array mask, this value will show the effective Cpu Ouputs Port Number

eHS Configuration Port Number: From the Communication Port Numbers array mask, this value will show the effective eHS Configuration Port Number

RST/Scenario Port Number: From the Communication Port Numbers array mask, this value will show the effective RST/Scenario Port Number

SineWaveGenerator DataIn port: This value must reflect the Data In port number of the FPGA Internal Sine wave generator that is dedicated to the eHS. It can be found in the *.conf file or in the firmware documentation.

Firmware Config Tab

The tab allows you to specify the configuration of the firmware used by eHS block to be set up. It will contextualized input and gate routing view.

Use a custom firmware configuration: By checking this option, the Custom input and gate source enumeration could be customized for specific firmware.

Custom input source enumeration: As a reminder, the default field is available for you to get the default value and associated valid format to provide.

Custom gate source enumeration: As a reminder, the default field is available for you to get the default value and associated valid format to provide.

Inputs

Inputs: This input port should be connected to vector signal, each element being one of the controlled inputs of the eHS solver (available when at least one "CPU Model" source type is selected in the eHS Input Configuration table). The required width is indicated on the port. Indices that do not correspond to a controlled voltage or current source are left unused. Please refer to the eHS Input Configuration table in the mask to identify the order of the inputs. The unit is Amps or Volts depending if a current or voltage source is driven.

Sine Wave Frequencies/Amplitudes/Phases/Offsets: This inport should be connected to vector signals, each element being one of the controlled parameter of the eHS solver's FPGA based Sine wave generators (available when at least one "Sine Wave Generator" source type is selected in the eHS Input Configuration table). Each must be a vector of double signal with the width display on the port. Each sine wave is generated following this equation: Output = Amplitude*SIN(2*pi*Freq*t + Phase*2*pi/360) + Offset
Frequencies are expected in Hz and specify the frequency of each sine wave generator channel.
Amplitudes are exected in Amps or Volts depending if the Sine wave generator is connected to a current or voltage source. They specify the gains applied on each sine wave generator channel.
Phases are exected in Degrees and specify the phase offset applied on each sine wave generator channel.
Offsets are exected in Amps or Volts depending if the Sine wave generator is connected to a current or voltage source. They specify the DC offset apply to each sine wave generator channel.

Gates: This inport should be connected to vector signal, each element being one of the controlled gates of the eHS solver (from "CPU Model" in the eHS Gate Configuration table). The required width is indicated on the inport. If you have specified the Use RT-EVENT check box, the input should be RTE signals with the number of event specified in the associated field. Otherwise Double format is required. Indices that do not correspond to a controlled gate are left unused. Please refer to the eHS Gate Configuration table in the mask to identify the order of the gates.

Scenario id: This input should be a scalar defining the scenario that the solver uses. When changing scenario, the set of component values used will be the one specified in the XLS file at the corresponding scenario lines. The default configuration is 0. The inputs values to load Scenarios1..N are 1..N. The input is saturated to the highest number of scenario thus if the maximum number of scenarios is 32, sending 34 to the input will load the scenario 32, and -1 will load 0.

Devices T: This input should be a vector containing the temperature for each device when the thermal loss feature is used. The order of this vector should match the Losses output port (First upper diode, first upper switch, first lower diode ...).

Reset: This input is a software reset and should be connected to a single signal of that state of the reset, 1 when the solver is in reset mode and 0 when the solver is not in reset mode. The reset input pin resets all states of the eHS block to their default values.

Outputs

Ouputs: This output is a vector, each element being one of the outputs of the solver. The width of the vector is equal to the number of measurements in the circuit. Note that the outputs of the eHS Gen4 block are the average values of the FPGA solver output over a CPU time step.

Losses: This output is a vector, each element gives the loss in watt for the different devices (First upper diode, first upper switch, first lower diode ...). Using a bus selector, you can get the name of each device.

Writing an XLS Scenario File

Example of an XLS scenario table for the boost converter shown above

Getting Started: The easiest way to write the first XLS file is to generate a template. To do so, the user can press the mask's button Generate a scenario file template from the Scenario Management tab or manually create the table. The first line, from B1 box, is reserved for RLC components declaration. The first column, from A2 box, is reserved for the scenarios declaration.

Filling the component line: The first line of the table, as of cell B1, is reserved for the component declaration. The component name is the netlist name from the top-level of the netlist (e.g. subsystem/componentname). If the component is inside a branch, its name will be the branch name with the suffixe .R, .L or .C, depending on the type of the targeted component.

Filling the scenario column: The first column of the table, as of cell A2, is the scenario declaration. Scenario labels must respect the naming convention Scenario followed by the scenario number. For example, the scenario number 21 right label will be Scenario21.

Default scenario line: The Default label is reserved to display the default values of each component. This is used for information only and not as actual netlist default values. Instead, the netlist file components values are used as default.

Removing lines/column: Removing lines (scenarios) and column (components) from the table is allowed. As a result, the removed scenarios and components will be kept at default values.

Filling the table: For each scenario, define the component parameters that need to be modified. Enter these scenario's component values in the table. Leaving an empty box will leave the component's value unchanged by the scenario. Thus it will keep its default value.

Number of modifications allowed by scenario: For each scenario, all declared components allow for their value to be modified. There is no limitation on the number of components that can be changed by a scenario.

Non-existing component: If a component is declared in the XLS table, but does not exist inside the netlist (wrong label/component removed), this column will be ignored, and will not have any effect on the scenario generation.

Non-existing scenario declaration: If a scenario is impossible (wrong label or scenario number greater than the maximum number of scenario feasible), an error will be thrown.

Verifying that the scenarios are well generated: If there is any issue with the scenario file the block will throw an error. To verify the number of scenario detected it is also useful to check the Number of Scenarios used in the Scenario tab of the mask.

Characteristics and limitations

Number of elements: The limitation on the number of elements (i.e. Sources, Gates, and Measurements) depends on the eHS form factor being used. For updated information on the limitations of each eHS Gen4 form factor, refer to the Specifications section of the User Guide.

• There is no limitation on the number of resistors.

• The solver time step is limited to approximately 4us.

• As many inductors and capacitors as necessary can be used so long as the timestep does not surpass the limit of approximately 4us.

• The use of Inductors, Capacitors and Switches has a strong impact on the minimum achievable timestep, whereas the use of inputs and outputs has a more limited impact.

Circuit design: See the product documentation and example models for details on how to design a circuit for use with the eHS.

Offline simulation: This block does not enable offline simulation. For offline simulation, use the eHS Offline simulation block in the eFPGASIM>>eHS and Converter Models>>Tools library. This block enables the developer to connect the block exactly as it is connected inside the FPGA, e.g. to a plant model, for more accurate results.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.