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eHS FPGA-based Power Electronics Toolbox
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Content
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Introduction
eHS Solver
Supported features
Latest Official Firmware Documentation
What's New in 2.21?
Workflows/Use case (Tutorials)
Using eHS with Schematic Editor
Quick start guide : Run a model on FPGA using the Schematic Editor
Block Library
Schematic Editor Block Library
SPS Block Library
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eHS Variable Load
Generic Machines
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Resolver Encoder Sensors
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Variable Load Parameter
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Variable Load Configurator
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24-Phase H-Bridge Inverter
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24-Phase Hysteresis Controller
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24-Phase Permanent-Magnet Synchronous Machine
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Analog Input Differential Rescaling Controller
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Analog Out Mapping Rescaling V2 Control Panel
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Chassis Selection
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Analog Out Mapping and Adjustments
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CPU stubline configuration
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Digital Output Mapping
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Dual Angle Sensors with faults CPU
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Dual eHS SPS
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Dual PMSM Motors SH v1
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Dual PMSM Motors SH Advanced Command
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Dual PMSM Motors SH v2
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Dual PMSM Motors VDQ Advanced Command
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Dual PMSM Motors VDQ
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Dual Vabc Test Sources Block
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eHS Data Convert for SFP
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eHS Gen3 SPS DEPRECATED
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eHS Offline simulation
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eHS Solver License Class
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eHSx32 for OP4200
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eHSx64 Command block
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Foster thermal network
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FPGA 2 inputs dot product configuration block
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FPGA 64-to-64 Interconnect Controller Block
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FPGA 64-to-64 Interconnect Controller Panel
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FPGA Discrete 1-Phase PLL
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FPGA First-Order Filter
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FPGA PI Controller
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FPGA PID Controller
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FPGA Second-Order Filter
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Generic High Speed Communication Block for eHS
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Generic Machines Induction Machine Model
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Generic Machines Permanent Magnet Synchronous Machine PMSM Model
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Generic Machines Synchronous Machine Model
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Induction Machine Command
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Inverter Solver with Boost Command
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Left side / Right side stubline
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Resolver Encoder Mapping
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RT-XSG Scope Series
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RT-XSG Scope Series Control
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Selectable Digital Input
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Selectable Digital Output
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Machine Interface Parallel to Parallel and Serial to Parallel Wrapper
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Solver Time Step Counter
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Switched-Reluctance Motor
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Switched Reluctance Motor Hysteresis Controller
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Switching function configuration
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Thermal losses feature
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Time-multiplexed Capacitor Differential Equation Solver Configuration
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Vabc Test Source
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eHS Frequency dependent line block
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Parallel to Parallel Interface
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Serial to Parallel Interface
Conf File writing Conventions
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eHS Gen4 SPS
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Half Line
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CPU Power Measurement Configuration
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Analog Out Mapping Rescaling V1 Control Panel
XSG Block library
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Quick start guide : Update a model on FPGA using the Schematic Editor
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User Notifications from FPGA Power Electronic Toolbox
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How to integrate eHS Block
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FPGA-based Power Electronics Toolbox Produced Content
How to tune eHS solver specific parameters
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How to integrate a firmware containing external models in the Schematic Editor
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How to tune machine snubbers
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eFPGASIM with RT-XSG Module - Rules and recommendations
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How to connect digital signals to eHS Gating Inputs with Schematic Editor
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How to create FPGA-based Custom Model compatible with Schematic Editor workflow
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How-to decouple eHS Gen5 circuit to improve minimum time step