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FPGA 64-to-64 Interconnect Controller Block - efs_cpuInterconnect64

Block


Table of Contents

Description

This block is used to control an FPGA 64-to-64 Interconnect block used to set dynamically the signal interconnections on FPGA. It should be connected to an FPGA 64-to-64 Interconnect Control Panel that will set this interconnection information according to the selected pattern.


Mask Parameters

Controller Name:Bind this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block The OpCtrl block controls initialization of the settings of one specific FPGA in the system.

LoadIn port number for interconnection information: Enter the number of the LoadIn port used to communicate the interconnection information for this block, in the range [1:32].


Inputs

XC_Cfg: This signal contains the interconnection information. It should be connected to the output of a "FPGA 64-to-64 Interconnect Control Panel" block.


Outputs

This block has no output.


Characteristics and limitations

This block has no special characteristics.

Direct FeedthroughNO
Discrete sample timeYES
XHP supportYES
Work offlineN/A


If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.

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