Description

This block allows the configuration and the control of a dual eHS solver to compute the outputs of a power-electronic circuit. The dual eHS is located on an FPGA-based board and runs at higher sample rate that the RT-LAB system.

The two circuits, one for each half of the solver, are typically created as a SPS model, and the block enables real-time control of its voltage and current sources as well as the gate signals of the switches.

Mask Parameters

Configuration tab

Controller name: Links this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block. The OpCtrl block controls initialization of the settings of one specific FPGA-based card in the system.

Number of eHS: This parameter sets whether this block controls both halves of the dual eHS solver or one half of it. Each half of the dual solver computes the outputs of an independent circuit. Circuit limitations in terms of number of elements can be found in the "Characteristics and limitations" section, below.

Maximum number of events for pulse control: This parameter sets the maximum number of transitions per calculation step on the switches. Its value needs to be at least equal to the maximal expected count of all transitions on any single gate input of the solver during one time step. This parameter is applied to both eHS solvers.

Sample Time: This parameter should be equal to the sample time of the real-time subsystem in which the block is located.

Generate eHS matrices: When this parameter is checked, the eHS matrices and related initialization files are generated when the block parameter is closed or upon clicking "Apply". After the matrices are generated, the checkbox is deselected automatically.

CommunicationPortNumbers: This parameter should reflect the 13-element series of communication ports used to communicate data between the real-time model and the hardware solver via the PCIe link. This information is found in the documentation of the I/O interfaces of the simulation system, and is system specific. Default is [2 3 4 2 3 11 12 13 14 15 16 2 3].

Use embedded signal generators to represent pure AC sources in the simulated circuit: If this option is selected, the fixed sources (DC, AC) in the circuit will be generated internally on the FPGA using embedded generators. If it is not selected, then the fixed sources will be considered as controlled sources, and will be controlled from the inputs of this block.

Source Signal Generators port numbers: This parameter should reflect the 2-element series of communication ports used to communicate data between the real-time model and the hardware solver embedded source signal generators via the PCIe link using LoadIn-type drivers. This information is found in the documentation of the I/O interfaces of the simulation system, and is system specific. Default is [4 5].

eHS1 tab

Circuit file name: Links this block to an file describing the circuit intended to be simulated using eHS. It should be a system built using the Simscape Electrical Specialized Power Systems (SPS) toolbox. See the product documentation and example models for details on how to design the circuit for use with eHS.

Switch source control: This parameter enables the developer do choose whether the simulated circuit switches should be controlled from this blocks inputs (i.e. "from RT-LAB") or from an internal FPGA signal. In the latter, the internal FPGA signal must be provided to the eHS core in the simulation platform firmware. Please refer to this firmware documentation for the availability and definition of such signal.

Switch source enumeration: This parameter is available only if the "Switch source control" parameter requires the control to be selected on a switch per switch basis. It should either be a scalar (applied to all switches in the circuit) or a vector enumerating the control, with indices 1 to 24 refering to SW01 to SW24 in the simulated circuit. For each element, the value determines whether the switches should be controlled from RT-LAB (this block, indicated as a "0") or from a signal internal to the FPGA (digital input or another internal signal, indicated as a "1").

Switch polarity: This parameter enables the developer do choose whether the simulated circuit switches should be active-high or active-low.

Switch polarity enumeration: This parameter is available only if the "Switch polarity" parameter requires the polarity to be selected on a switch per switch basis. It should either be a scalar (applied to all switches in the circuit) or a vector enumerating the polarity, with indices 1 to 24 refering to SW01 to SW24 in the simulated circuit. For each element, the value determines whether the switches should be active-high (indicated as a "0") or active-low (indicated as a "1").

Provide explicit sample time for solver eHS2: If this option is selected, the next field is made available to set the solver sample time. The minimal solver sample time depends on the complexity of the circuit, and typically ranges in the hundreds of nanoseconds. This may be helpful for:

• Accelerating the offline simulation, because for offline simulation the step size has to be set to the greatest common divisor of the eHS step size and the real-time (RT-LAB) system step size (down to 5 ns without setting an explicit sample time).
• Synchronizing 2 eHS modules to the same sample time
• Testing different sample times

Sample time for eHS1: This parameter shows the sample time of the solver. By default, it is set to the minimal sample time achievable, and is editable only if the "Provide explicit sample time for solver eHS1" option is selected. In that case, a warning is displayed if the sample time entered is shorter than the minimal sample time calculated for the circuit to solve.

Voltage/current controlled sources provision: This parameter enables the developer do choose whether the simulated circuit inputs should be controlled from this blocks inputs (i.e. "from RT-LAB") or from an internal FPGA signal. In the latter, the internal FPGA signal must be provided to the eHS core in the simulation platform firmware. Please refer to this firmware documentation for the availability and definition of such signal.

Voltage/current source control enumeration: This parameter is available only if the "Voltage/current controlled sources provision" parameter requires the control to be selected on a input per input basis. It should either be a scalar (applied to all inputs in the circuit) or a vector enumerating the source control setting, with indices 1 to 16 refering to U01 to U16 in the simulated circuit. For each element, the value determines whether the input should be controlled from RT-LAB (this block, indicated as a "0") or from a signal internal to the FPGA (analog input or another internal signal, indicated as a "1").

Gs: This parameter is the conductance of the switches of the circuit. If it is a scalar, this value is applied to all switches in the circuit. If it is a vector, each element is applied to the switch with the corresponding index in the circuit to be solved. This parameter is available only if the "Show advanced settings for eHS1 solver" option is selected.

Initial switch voltage enumeration: This parameter is used to specify the initial value of the state variables corresponding to the switches in the circuit. It represent the initial voltage of the capacitor model of the open switch, if the switch is initially open. If it is a scalar, this value is applied to all switches in the circuit. If it is a vector, each element is applied to the switch with the corresponding index in the circuit to be solved. This parameter is available only if the "Show advanced settings for eHS1 solver" option is selected.

Initial switch current enumeration : This parameter is used to specify the initial value of the state variables corresponding to the switches in the circuit. It represent the initial current of the inductor model of the closed switch, if the switch is initially closed. If it is a scalar, this value is applied to all switches in the circuit. If it is a vector, each element is applied to the switch with the corresponding index in the circuit to be solved. This parameter is available only if the "Show advanced settings for eHS1 solver" option is selected.

eHS2 tab

The parameters of eHS2 are similar to eHS1 parameters.

Inputs

U eHS 1: This input should be a vector, each element being one of the controlled inputs of the eHS1 solver. The width of the vector should be equal to the sum of all U inputs (voltages, currents) present in the circuit. Indices that do not correspond to a controlled voltage or current source are left unused.

C eHS 1: This input should be a vector, each element being one of the switch gates of the eHS1 solver. The width of the vector should be equal to the sum of all SW switches in the circuit, and the format of each gate signal should be of RTE type.

Reset 1: This input is a software reset for solver eHS1. When set to "1", the solver is in the reset mode. When set to "0", the solver is not in the reset mode.

The inputs of eHS2 are similar to eHS1 inputs.

Outputs

Y eHS 1: This output is a vector, each element being one of the outputs of the eHS1 solver. The width of the vector is equal to the sum of all Y outputs (voltages, currents) present in the circuit.

The outputs of eHS2 are similar to eHS1 outputs.

Characteristics and limitations

Number of elements: The circuit is subject to the following limitations:

• The maximum number of inputs (currents or voltages) in the circuit is sixteen (16) elements.
• The maximum number of switching devices (IGBT/Diode, Diode, Ideal switch, Breaker) is twenty-four (24) elements.
• The maximum number of non switching devices (capacitors, inductances) is set to the difference (63-U-S), where U and S are the number of inputs and switches, respectively.
• There is no limitation on the number of resistors.

Circuit design: See the product documentation and example models for details on how to design the circuit for use with eHS.

Offline simulation: This block does not enable offline simulation. For offline simulation, use the appropriate block in the eFPGASIM RT-LAB Converter Tools library. This block enables the developer to connect the block exactly as it is connected inside the FPGA, e.g. to a plant model, for more accurate results. One offline block should be added for each solver, eHS1 and eHS2, and connections between the two should be made manually by the developer.

Communication delays: The outputs of the solver computed on the hardware at a certain time step are made available in the Y outputs two simulation steps later. This means that the feedback comes three simulation steps after a command is sent on the U inputs. The solver sample time applies only to the computations that take place on the hardware on which the eHS solver is placed.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.