Documentation Home Page eHS Toolbox Home Page
Pour la documentation en FRANÇAIS, utilisez l'outil de traduction de votre navigateur Chrome, Edge ou Safari. Voir un exemple.

Dual Vabc Test Sources Block - efs_cpuDualVabcTestSources

Block


Table of Contents

Description

This block handles the communication with the FPGA Dual Vabc Test Source.

The Dual Vabc FPGA source is a sinus and pwm generator.

For each motor Vabc :

Va = SourceAmp*cos(elec_angle_motor + SourceAngleDeg)

Vb = SourceAmp*cos(elec_angle_motor + SourceAngleDeg - 120deg)

Vc = SourceAmp*cos(elec_angle_motor + SourceAngleDeg + 120deg)

The PWM signals are generated from these same reference in exception of the SourceAmp which is replaced by the modulation index.

This source is only used for tests and debug of the FPGA model or users configuration. In normal operation mode (Motor model Controlled by a real external controller), this blocks is not mandatory in the RT-Lab model.


Mask Parameters

Controller Name: Links this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block. The OpCtrl block controls initialization of the settings of one specific FPGA-based card in the system.

Block Index: This parameter is a positive integer used to identify the block.

Data In Port Number: This should reflect the LoadIn port used to configure the machine used in the FPGA.

Load In Port Number: This should reflect the LoadIn port used to configure the machine used in the FPGA.

Data Out Port Number: This should reflect the DataOut port used to receive the block data from the FPGA.


Inputs

SourceAngleDeg (1 & 2): This represents the angle from the source in degrees.

SourceAmp (1 & 2): This represents the voltage amplitude from the source.

Modulation Index (1& 2): A number between 0 and 1 that represents the amplitude of the dutycycle.

Deadtime (1 & 2): This represents the deadtime applied between the upper and lower pulse-width modulation (pwm).

f pwm_hz (1 & 2):This represents the carrier frequency in Hertz (Hz)

DutyOverridePort (1 & 2): A feature that force the dutycycle to override the modulation index. It requires a bus signal with the values ForceDuty A, B and C and the ForceDutyEnabler A, B and C.


Outputs

Source Out (1 & 2): This output returns the values for the voltages A, B and C as well as the pwm.


Characteristics and limitations

Direct FeedthroughNO
Discrete sample timeYES
XHP supportYES
Work offlineN/A


If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.

OPAL-RT TECHNOLOGIES, Inc. | 1751, rue Richardson, bureau 1060 | Montréal, Québec Canada H3K 1G6 | opal-rt.com | +1 514-935-2323
Follow OPAL-RT: LinkedIn | Facebook | YouTube | X/Twitter