Description

This block allows the configuration and the control of a eHSx64 solver to compute the outputs of a power-electronic circuit. The eHSx64 core is located on an FPGA-based board and runs at higher sample rate that the RT-LAB system.

The netlist file can be either a Simscape Electrical Specialized Power Systems (SPS) or Plecs simulink model (.mdl), a PSIM netlist (.psimsch) or a Multisim netlist (.xml).

The block enables real-time control of its voltage and current sources as well as the gate signals of the switches.

In addition, it does the scenario management of the netlist.

Mask Parameters

Circuit tab

Generate eHS matrices: When this parameter is checked, the eHS matrices and related initialization files will be generated after the user will click on "OK" or "Apply". After the matrices are generated, the checkbox is deselected automatically. Note that the previous solver configuration files will be overwritten.

Circuit file name: Links this block to an file describing the circuit intended to be simulated using eHS. It should be a system built using the SPS toolbox. See the product documentation and example models for details on how to design the circuit for use with eHS.

Provide explicit sample time for solver eHS: If this option is selected, the next field is made available to set the solver sample time. The minimal solver sample time depends on the complexity of the circuit, and typically ranges in the hundreds of nanoseconds.

This may be helpful for:

• Accelerating the offline simulation, because for offline simulation the step size has to be set to the greatest common divisor of the eHS step size and the real-time (RT-LAB) system step size (down to 5 ns without setting an explicit sample time).
• Testing different sample times
• Reduce the quantization error for systems that contain very large time constants (>> 10sec)
• Synchronize eHS with another FPGA solver core

Show advanced settings for eHS solver: This checkbox allows the user to modify Gs, Switch initial voltage and current. If unchecked, the last entered configuration of these parameters will be use.

Gs: This parameter is the conductance of the switches of the circuit. If it is a scalar, this value is applied to all switches in the circuit. If it is a vector, each element is applied to the switch with the corresponding index in the circuit to be solved.

Initial switch voltage enumeration: This parameter is used to specify the initial value of the state variables corresponding to the switches in the circuit. It represent the initial voltage of the capacitor model of the open switch, if the switch is initially open. If it is a scalar, this value is applied to all switches in the circuit. If it is a vector, each element is applied to the switch with the corresponding index in the circuit to be solved.

Initial switch current enumeration : This parameter is used to specify the initial value of the state variables corresponding to the switches in the circuit. It represent the initial current of the inductor model of the closed switch, if the switch is initially closed. If it is a scalar, this value is applied to all switches in the circuit. If it is a vector, each element is applied to the switch with the corresponding index in the circuit to be solved.

Infos tab

This tab gathers the last valid netlist overall information.

You could find the netlist name, the achievable minimum time step, the number and enumeration of inputs (sources) outputs (measurements) and switches, and also the number of states to be computed.

It is especially helpful to verify that the sources, measurements and switches order has been read as expected by the user from the netlist file. This order is critical to get the right input, output and gates assignation.

Inputs Settings tab

Voltage/current controlled sources provided: This parameter enables the developer do choose whether the simulated circuit inputs should be controlled from this blocks inputs (i.e. "Constant from RT-LAB" or "FPGA Sine Wave Generator controlled by RT-Lab block") or from an internal FPGA signal ("Loopback from a second eHS Outputs" or "From Internal FPGA Signals"). In the latter ones, the internal FPGA signal must be provided to the eHS core in the simulation platform firmware. Please refer to this firmware documentation for the availability and definition of such signal. The sources' controllers can be assign independently using the option "Independent Setting for each element".

Voltage/current source control enumeration: This setting is available when previous parameter is set to "Independent Setting for each element" only. It allows the user to route the inputs' sources independently for each input element.
There is up to 32 inputs, so it is required to enter a 32 elements vector. Each element will be used to route the right source to the corresponding input.
If a 0 is set, then the corresponding input will be driven by the RT-Lab input port.
If a 1 is set, it will be driven by the embedded sine wave generator.
If a 2 is set, it will be driven by an output of a second eHS.
If a 3 is set, another internal FPGA signal will drive the input.

Use as many inputs as the current netlist requires: When enabled, this option will perform a netlist analysis, to determine how many inputs are required, and will set the "Number of inputs used" parameter accordingly.

Number of inputs used: This parameters sets the number of inputs that will be send to the FPGA core. In order to limit the communication overhead and enhance the real time performance, it is advised to use as few inputs as possible.
Note that the size of the signal driving the block "INPUTS" and sine wave generator ports must comply with the number of inputs specified.
For example, if 16 inputs are enabled, only a vector of 16 values can be connected to "INPUTS" port. Also 16 frequencies, amplitudes and phase must be provided to the Sine Wave Generator ports.

Use embedded Sine Wave Generators: The eHSx64 package contains a 32-channel Sine Wave Generator embedded inside the FPGA. It can be used to replace the standards inputs from RT-LAB.
The sine wave generator has a fine resolution (down to 140ns) which is much better than a typical RT-LAB model time step (10-100us), the rate at which the standard inputs are updated.
Three input ports will be added to the RT-Lab block in order to drive the frequency, amplitude and phase of each sine generator channel.

Sine Wave Generators LoadIn port number: When the sine wave generators are enabled, the user must provide the LoadIn port number to communicate with the generators. With the standard firmware provided with ePFGAsim, the default port number is 3.

Gates Settings tab

Switch source control: This parameter enables the developer do choose whether the simulated circuit switches should be controlled from this blocks inputs (i.e. "from RT-LAB") or from an internal FPGA signal. In the latter, the internal FPGA signal must be provided to the eHS core in the simulation platform firmware. Please refer to this firmware documentation for the availability and definition of such signal.

Switch source enumeration: This parameter is available only if the "Switch source control" parameter requires the control to be selected on a switch per switch basis. It should either be a scalar (applied to all switches in the circuit) or a vector enumerating the control, with indices 1 to 64 referring to SW01 to SW64 in the simulated circuit. For each element, the value determines whether the switches should be controlled from RT-LAB (this block, indicated as a "0") or from a signal internal to the FPGA (digital input or another internal signal, indicated as a "1").
Note: this parameter must be a 64-element vector even if not all of the 64 switches are used.

Number of gates from RT-Lab: Number of gate's signals, controlled by this block (i.e. "from RT-LAB"), that are enabled. The gate number will be shared by the RTE gates and static gates.

RTE Gates: Gates range that will be controlled by the "Gates RTE" input port of this block.
A RTE signal allows to create digital signal that will perform transitions during a CPU time step at specified times.
In opposition, a static digital signal is sampled at the beginning of next CPU time step and is latch for the duration of this time step.
If "none" is selected, the "Gates RTE" input port will be removed.
If less than the total number of gates is selected, a "Gates Static" input port will be added. The gates that are not in the range defined by this parameter will be controlled by the "Gates Static" input port.
Otherwise, the "Gates Static" input port will be removed from the block, all the gates activated will be accessible by the "Gates RTE" input port.

Maximum number of events for pulse control: This parameter sets the maximum number of transitions per calculation step on the switches. Its value needs to be at least equal to the maximal expected count of all transitions on any single gate input of the solver during one time step. This parameter is applied to all RTE digital signal generators.

Static Gates: This parameters gives the information of the gates that will be driven by this block's "Gates Static" input port.

Switch polarity: This parameter enables the developer do choose whether the simulated circuit switches should be active-high or active-low.

Switch polarity enumeration: This parameter is available only if the "Switch polarity" parameter requires the polarity to be selected on a switch per switch basis. It should either be a scalar (applied to all switches in the circuit) or a vector enumerating the polarity, with indices 1 to 64 referring to SW01 to SW64 in the simulated circuit. For each element, the value determines whether the switches should be active-high (indicated as a "0") or active-low (indicated as a "1").

Scenario Management tab

The scenario feature allows the user to define multiple set of values for the netlist RLC components. For each scenario, the user will be able to modify the values of the components.

Enable scenarios: By checking this option, the scenario feature will be enable.

XLS File name: The XLS file contains the table of RLC components values depending on the scenario number. This parameter gives the path of the file that will be use to perform the scenario declaration.

Command: Option "Create a XLS template for the current netlist": this option will create a template file at the name and location set in the "XLS File name" GUI input.
Option "Update eHS configuration file with current scenarios": this option will update the eHS configuration matfile with the scenarios declared in the current disk version of the XLS file.

XLS active sheet number: The scenario feature supports multiple sheets in the xls file as soon as each sheet format is conform to the "Make a Scenario XLS file" tutorial description. The sheet number must be a positive non-null integer. The sheet must exist for the reading operation to succeed.

Maximum number of scenarios available with current netlist: This is the information of the number of scenario available for the current netlist. This number takes into account the default values scenario that can not be modified.

Comm Settings tab

Controller name: Links this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block. The OpCtrl block controls initialization of the settings of one specific FPGA-based card in the system.

Sample Time: This parameter should be equal to the sample time of the real-time subsystem in which the block is located.

CommunicationPortNumbers: This parameter should reflect the 13-element series of communication ports used to communicate data between the real-time model and the hardware solver via the PCIe link.
Element 1= load in port number for eHS initialisation
Element 2= load in port number for eHS configuration
Element 3= data in port number for eHS inputs from CPU
Element 4 to 10= data in port number for eHS TSDO generators (RTE gates)
Element 11 to 12= data out port number for eHS outputs to CPU
This information is found in the documentation of the I/O interfaces of the simulation system or in the rt-xsg source model of the bitstream, and is system specific. Default is [1 2 1 2 3 4 5 6 7 8 9 1 2].

Inputs

INPUTS: This input should be a vector, each element being one of the controlled inputs of the eHS solver. The width of the vector should correspond to the "Number of inputs used" parameter of this block's mask. Indices that do not correspond to a controlled voltage or current source are left unused.

SinWaveGen Freqs|Amplitudes|Phases: This input should be a vector, each element being one of the frequency/amplitude/phase of a Sine Wave Generator. The width of the vector should correspond to the "Number of inputs used" parameter of this block's mask. Indices that do not correspond to a controlled voltage or current source are left unused.

GATES RTE: This input should be a vector, each element being one of the switch gates of the eHS solver. The width of the vector should correspond to the size of the range assigned in the "RTE Gates" parameter of this block's mask. The format of each gate signal should be of RTE type, with the number of event set in the GUI.

GATES STATIC: This input should be a vector, each element being one of the switch gates of the eHS solver. The width of the vector should correspond to the size of the range displayed in the "Static Gates" parameter of this block's mask. The format of each gate signal should be of double type.

SCENARIO_ID: This input should be a scalar, the value gives the scenario that the solver runs. When changing scenario, the set of component values used will be the one specified in the XLS file, at the corresponding scenario lines. Default configuration is 0. The inputs values to load Scenario1..N are 1..N. The input is not overflow protected, thus if the maximum number of scenario is 32, sending 34 to the input will load the scenario3.

Reset: This input is a software reset. When set to "1", the solver is in the reset mode. When set to "0", the solver is not in the reset mode.

Write a XLS scenario file

Example of a xls scenario table for the boost converter shown at the top

Getting Started: The easiest way to write the first XLS file is to generate a template. To do so, the user can use the command "Create a XLS template for the current netlist" of the scenario management tab. The user can also write him self the table. The first line, from B1 box, is reserved for RLC components declaration. The first column, from A2 box, is reserved for the scenarios declaration.

Filling the component line: The first line of the table, from the box B1, is reserved for the component declaration. The component name is the netlist name (from the top level of the netlist. example: "subsystem/componentname"). If the component is inside a branch, its name will be the branch name with the suffixe ".R", ".L" or ".C", depending on the type of the targeted component.

Filling the scenario column: The first column of the table, from the box A2, is the scenario declaration. Scenario labels must respect the naming convention "Scenario" followed by the scenario number. As an example, the scenario number 21 right label will be "Scenario21".

Default scenario line: "Default" label is reserved to display the default values of each component (for information only, they are not used as netlist default values, the netlist file components values are).

Removing lines/column: Removing lines (scenarios) and column (components) from the table is allowed. As a result, the removed scenarios and components will keep the default values.

Filling the table: For each scenario, define the component parameters that need to be modified. Enter these scenario's component values in the table. Leaving an empty box will leave the component's value unchanged by the scenario. Thus it will keep its default value.

Number of modifications allowed by scenario: For each scenario, all components that are declared can have their value modified. There is not limitation of component number that can be affected by a scenario.

Non-existing component: If a component is declared in the XLS table, but does not exist inside the netlist (wrong label/component removed), this column will be ignored, and will not have any effect on the scenario generation.

Non-existing scenario declaration: If a scenario is impossible (wrong label or scenario number greater than the maximum number of scenario feasible), an error will pop-up.

Verifying the scenario are well generated: While generating eHSx64 configuration, a log is generated in Matlab command prompt to let the user know what are the effective changes made to the netlist depending on the scenario number.

Log corresponding to the boost converter scenario table

Outputs

OUTPUTS: This output is a vector, each element being one of the outputs of the solver. The width of the vector is 32. Note that the outputs of eHSx64 are the average values of the FPGA solver output at the end of the preceding CPU time step.

Characteristics and limitations

Number of elements: The circuit is subject to the following limitations:

• The maximum number of inputs (currents or voltages) in the circuit is thirty-two (32) elements.
• The maximum number of switching devices (IGBT/Diode, Diode, Ideal switch, Breaker) is sixty-four (64) elements.
• There is no limitation on the number of resistors.
• The usage of Inductors, Capacitors and Switches has a strong impact on the minimum time step achievable. The usage of inputs and outputs has a more limited impact though.

Circuit design: See the product documentation and example models for details on how to design the circuit for use with eHS.

Offline simulation: This block does not enable off-line simulation. For off-line simulation, use the appropriate block in the eFPGASIM RT-LAB Converter Tools library. This block enables the developer to connect the block exactly as it is connected inside the FPGA, e.g. to a plant model, for more accurate results.

Communication delays: The outputs of the solver computed on the hardware at a certain time step are made available in the Y outputs two simulation steps later. This means that the feedback comes three simulation steps after a command is sent on the U inputs. The solver sample time applies only to the computations that take place on the hardware on which the eHS solver is placed.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.