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Common Event Detector




The Event Detector block is used to return information describing rising-edge and falling-edge transitions (or events) occurring on digital input channels of a carrier connected to an FPGA.

Each transition is described by the ending state of the digital line (0 for a falling edge, and 1 for a rising edge), and the time, relative to the beginning of the calculation step, when the transition occurred.

The data values are transferred from the FPGA to the RT-LAB model through one DataOut port of the bitstream, via the PCIe bus of the target computer.

Each FPGA bitstream using digital input channels in Event Detector mode comes with a configuration file which lists the Data port number and the corresponding carrier location in the system. The configuration file name is the same as the bitstream file name entered in the OpCtrl block, with the extension .conf instead of .bin.

This configuration file uses three parameters to describe the location of the carrier channels:

  • the Slot number (in the range 1 to 4) is the slot of the backplane connected to the system in which the carrier is installed,
  • the Section A or B is a subset of 32 lines of the carrier. For example, with the 32 In/32Out OP4510 carriers, section A refers to the 32 input lines and section B to the 32 output lines,
  • the Sub-Section, 1 to 4, is a subset of 8 channels connected to one DataOut port: subset 1 represents the 8 first channels of one section of the carrier, subset 2 represents the 8 next channels, etc.

The user must refer to the configuration file (opened with any text editor) for selecting the DataOut port number for the desired digital input channels. The Event Detector block then parses the configuration file and displays the Slot, Section and Sub-section values corresponding to the DataOut port number in the 'Slot infos' parameter.

The maximum number of digital input channels controlled by one Event Detector is limited by the size of the subset of channels in one sub-section which is fixed to 8 in the current implementation.

The maximum number of transition data returned by the DataOut port is set to 250 in the current implementation. This is the total number of transitions that can be reported for the group of 8 channels connected to that DataOut port. In order to decrease data transfer times between the FPGA and the model, the user can decrease the number of transition information returned to the model to the actual expected number of transitions per calculation step, with the use of the 'Expected number of events per channel' parameter.


ControllerNameBind this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block The OpCtrl block controls initialization of the settings of one specific FPGA in the system.
DataOut port numberEnter the number of the DataOut port to be controlled by this block, in the range [1:64] for the VC707 and TE0741 FPGAs and [1:32] for all others.
Slot infosThis non-editable parameter displays the physical location of the digital input channels related to the selected DataOut port, as obtained from the parsing of the configuration file.
Maximum number of channels controlled by this blockThis non-editable parameter displays the number of channels in one sub-section listed in the configuration file, typically 8.
Number of channelsEnter the number of channels for which data values will be returned at each calculation step. This number must be less than or equal to the value of the 'Maximum number of channels' parameter. The data transfer mechanism between RT-LAB and the FPGA does not allow the selection of individual channels in the sub-section of channels. The data returned by the block will thus correspond to the N first channels of the sub-section, where N is the value of the 'Number of channels' parameter.
Expected number of events per channelThis parameter controls the amount of transition data transferred from the FPGA to the RT-LAB model at each calculation step. If the value entered is a single integer value, it applies to all channels. The value can also be entered as a vector of values, each element of the vector specifying the number of events for one channel. This parameter is used to set the widths of the States and Times outputs.
Time unitSelect the time unit of the Times output values. If 'Time ratio' is selected, the Times values returned to represent the ratio of the transition time relative to the beginning of the calculation step, over the duration of the step. If 'Seconds' is selected, the Time values represent the delay between the beginning of the calculation step and the time of the occurrence of the transition.
Sample Time (s)This parameter allows the user to specify the block sample time in seconds. The default value is 0, which specifies a continuous sample time (note that the sample time is borrowed from the separated subsystem) while -1 specifies an inherited sample time. A functionality block and its associated controller block must execute at the same sample time.


This block has no inputs.


This block has one States and one Times output for each channel, plus one global Status output.

States and Times outputs return values in chronological order, i.e. the first value of each States and Times vectors corresponds to the first transition that occurred on the digital input channel during the previous calculation step, the second value to the second transition etc.

The outputs can take the following values:


Possible Values Description 
1Rising edge transition detected 
0Falling edge transition detected
-1No transition occurred


Possible Values (time ratio) Description 
0 <= x < 1 Ratio of the time of occurence of the transition (Ttr) over the duration of the calculation step (Ts). Ttr is the time offset of the transtion relative to the beginning of the calculation step where the transition occured : Ttr = [0:Ts]; and x = Ttr / Ts 
1No transition occurred 
Possible Values (seconds) Description 
0 <= x < Ts Time elapsed between beginning of calculation step and occurrence of transition
Ts No transition occurred 


0No error.

Block could not be matched with an OpCtrl block (check the 'controller Name' value), or FPGA card initialization problem.

-2Data reception timeout. This error can be caused by model synchronization errors,

Data reception error : the block received less data from the FPGA card than the value expected according to the 'Expected number of events' parameter. Missing data were replaced by 0.


Data reception error : the block received more data from the FPGA card than the value expected according to the 'Expected number of events' parameter. Extra data were discarded.

Characteristics and Limitations

PWM Processing

When the Event Detector block is used to capture PWM signal, processing time increases with the number of events to decode so it increases with the PWM frequency and the number of channels. The amount of data transferred between the FPGA and CPU also increases with the number of events since the transition times must be transferred for each step.

Connector Pin Assignments

The user should refer to the documentation of the carrier for connector pin assignments.

Direct FeedthroughNo
Discrete sample timeYes
XHP supportYes
Work offlineNo

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