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Common Encoder Out




The Encoder Out block is used to produce Quadrature Encoder output signals (A, B, and the index signal Z) on the digital output lines of an carrier connected to an FPGA card.

The encoder signals frequency values are transferred to the FPGA from the RT-LAB model through one DataIn port of the bitstream, via the PCIe bus of the target computer.

Each FPGA bitstream using digital output channels in Encoder Out mode comes with a configuration file which lists the DataIn port numbers and their corresponding carrier location in the system. The configuration file name is the same as the bitstream file name entered in the OpCtrl block, with the extension .conf instead of .bin.

This configuration file uses three parameters to describe the selection of the carrier channels :

  • the Slot number (in the range 1 to 4) is the slot of the backplane connected to the system in which the carrier is installed
  • the Section A or B is a subset of 32 lines of the carrier. For example, with the 32 In/32Out OP4510 carrier, section A refers to the 32 input lines and section B to the 32 output lines
  • the Sub-Section, 1 to 4, is a subset of 8 data values connected to the port: subset 1 returns values for the 8 first channels of one section of the carrier, subset 2 returns values for the 8 next channels, etc.

The user must refer to the configuration file for selecting the port number for the desired digital output channels. The Encoder Out block then parses the configuration file and displays the Slot, Section and Sub-section values corresponding to the port number in the 'Slot infos' parameter.

The maximum number of digital output channels controlled by one Encoder Out is limited by the size of the subset of channels in one sub-section, which is fixed to 2 in the current implementation.


ControllerNameBind this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block The OpCtrl block controls initialization of the settings of one specific FPGA card in the system.
DataIn port numberEnter the number of the DataIn port to be controlled by this block, in the range [1:64] for the VC707 and TE0741 FPGAs and [1:32] for all others.
Slot infosThis non-editable parameter displays the physical location of the digital output channels related to the selected DataIn port, as obtained from the parsing of the configuration file.
Maximum number of Encoder signals controlled by this blockThis non-editable parameter displays the number of channels in one sub-section listed in the configuration file.
Number of Encoder signalsEnter the number of signals for which encoder frequency values will be transmitted at each calculation step. Each encoder signal is a set of A, B and Z signals. The value of the number of signals must be less than or equal to the value of the 'Maximum number of Encoder signals' parameter. The data transfer mechanism between RT-LAB and the FPGA does not allow the selection of individual channels in the sub-section of channels. The data returned by the block will thus apply to the N first channels of the sub-section times 3, where N is the value of the 'Number of channels' parameter, and 3 stands for the A, B and Z signals.
Frequency unitSelect between 'Hz' or 'rpm' unit for the frequency values supplied via the input of the block. Note that the current implementation is limited to a maximum frequency of 10000 rpm, or 166.66 Hz.
ModeSelect between a single-ended or differential mode for the output signal. This parameter is not supported yet. Default value is single-ended.
Resolution (# of cycles per revolution)Enter the integer number of cycles of the A and B signals per revolution. Its maximum is 32767 cycles per revolution. However, the maximum resolution combined with high rates will lead to precision loss. The maximum guaranteed resolution is 25000 PPR.
Clockwise rotationThis parameter determines whether the encoder signals are produced with signal A leading signal B, or the reverse, in a clockwise rotation.


The block has one inport, named Hz or rpm, depending on the value of the 'Frequency unit' parameter.
The size of the inport is determined by the 'Number of Encoder signals' parameter. One frequency value must be supplied for each set of A,B,Z encoder signals.

The direction of the signal depends on the sign of the frequency value. The frequency range is thus [-10000;+10000] rpm, i.e. [0;10000] rpm in positive or negative direction. Out of range values get saturated to these values.


The Status output returns the following values:

0No error.

Block could not be matched with an OpCtrl block (check the 'controller Name' value), or FPGA card initialization problem.

-2Internal memory initialization problem.

Characteristics and Limitations

Direct FeedthroughNo
Discrete sample timeInherited
XHP supportYes
Work offlineNo

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