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Common PWM In




The PWM In block is used to retrieve Duty cycle and Frequency values from Pulse Width Modulated signal connected to digital input lines of an carrier connected to an FPGA.

The period and the duty cycle values are transferred from the bitstream to the RT-LAB model through the DataOut port allocated to the PWM In, via the PCIe bus of the target computer; a quick processing by the PWM In is made to supply the frequency and the duty cycle.

The PWMI driver measures the duty cycle and carrier frequency using the relation between the rising and falling edges of the input signal. When the input is not switching (for example when the duty cycle is 0 or 1), the driver cannot establish whether it's the frequency that became slower or the duty cycle that is 0 or 1, until it reaches a supported timeout.
Therefore the equation for the duty cycle is: 

Each FPGA bitstream using digital input channels comes with a configuration file; this file lists the Data port number and their corresponding carrier location in the system. The configuration file name is the same as the bitstream file name entered in the OpCtrl block, with the extension .conf instead of .bin.

This configuration file uses three parameters to describe the selection of the carrier channels:

  • the Slot number (in the range 1 to 4) is the slot of the backplane connected to the system in which the carrier is installed,
  • the Section A or B is a subset of 32 lines of the carrier. For example, with the 32 In/32Out OP4510 carrier, section A refers to the 32 input lines and section B to the 32 output lines,
  • the Sub-Section, 1 to 4, is a subset of 8 data values connected to the port: subset 1 returns values for the 8 first channels of one section of the carrier, subset 2 returns values for the 8 next channels, etc.

The user must refer to the configuration file for selecting the port number for the desired digital input channels. The PWM In block then parses the configuration file and displays the Slot, Section and Sub-section values corresponding to the port number in the 'Slot infos' parameter.

The DataOut ports connected to Pulse Width Modulation input signals are identified by the acronym 'PWMI' in the configuration file.

The maximum number of digital input channels controlled by one PWM In is limited by the size of the subset of channels in one sub-section, which is fixed to 8 in the current implementation.


Controller NameBind this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block The OpCtrl block controls initialization of the settings of one specific FPGA in the system.
DataOut port numberSet the number of the DataOut port to be controlled by this block, in the range [1:64] for the VC707 and TE0741 FPGAs and [1:32] for all others.
Slot infosThis non-editable parameter displays the physical location of the digital input channels related to the selected DataOut port, as obtained from the parsing of the configuration file.
Available channelsThis non-editable parameter specifies the maximum number of PWM lines supported by the DataOut port as defined in the RT-XSG bitstream.
Number of PWM linesSet the number of PWM channels to be used by the block. The value must be less than or equal to the value of the 'Available channels' parameter. Only the first channels will be measured by the block.
Sample time (s)This parameter allows the user to specify the block sample time in seconds. The default value is 0, which specifies a continuous sample time (note that the sample time is borrowed from the separated subsystem) while -1 specifies an inherited sample time. A functionality block and its associated controller block must execute at the same sample time.


This block has no inputs.


The block has three (3) outports.

HzThis outport returns the frequency of PWM signal; it is specified Hz. A null value is returned when the line is unconnected. The minimal frequency measured is 100 Hz.
DutyThis outport is the duty cycle of PWM signal. A null value is returned when the line is unconnected.
StatusThe Status output returns the following values:

0No error.

Block could not be matched with an OpCtrl block (check the 'controller Name' value), or FPGA initialization problem.

-2Data reception timeout. This error can be caused by model synchronization errors,

Data reception error: the block received fewer data from the FPGA than the value specified in the 'Data outport width' parameter. Missing data were replaced by 0.


Data reception error: the block received more data from the FPGA than the value specified in the 'Data outport width' parameter. Extra data were discarded.

Characteristics and Limitations

Unexpected behavior: When the duty cycle value returned from bitstream is non-null and the period is null, negative values are outputted. This behavior could be explained by a wrong bitstream file.

Block limitations: The frequency of PWM signal should be between 100 Hz to 190 Khz to ensure the correct functionality.

Direct FeedthroughNo
Discrete sample timeYes
XHP supportYes
Work offlineNo

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