Block

Mask

Description

The Event Generator block is used to transmit informations describing rising-edge and falling-edge transitions (or events) to be applied to digital output channels of a carrier connected to an FPGA.

Each transition is described by the ending state of the digital line (0 for a falling edge, and 1 for a rising edge), and the time, relative to the beginning of the calculation step, when the transition is to occur.

The data values are transferred to the FPGA bitstream from the RT-LAB model through one DataIn port of the bitstream, via the PCIe bus of the target computer.

Each FPGA bitstream using digital output channels in Event Generator mode comes with a configuration file which lists the Data port number and the corresponding carrier location in the system. The configuration file name is the same as the bitstream file name entered in the OpCtrl block, with the extension .conf instead of .bin.

This configuration file uses three parameters to describe the selection of the carrier channels:

the Slot number (in the range 1 to 4) is the slot of the backplane connected to the system in which the carrier is installed,
the Section A or B is a subset of 32 lines of the carrier. For example, with the 32 In/32Out OP4510 carrier, section A refers to the 32 input lines and section B to the 32 output lines,
the Sub-Section,1 to 4, is a subset of 8 data values connected to the port: subset 1 returns values for the 8 first channels of one section of the carrier, subset 2 returns values for the 8 next channels, etc.

The user must refer to the configuration file (opened with any text editor) for selecting the port number for the desired digital output channels. The Event Generator block then parses the configuration file and displays the Slot, Section and Sub-section values corresponding to the port number in the 'Slot infos' parameter.

The maximum number of digital output channels controlled by one Event Generator is limited by the size of the subset of channels in one sub-section which is fixed to 8 in the current implementation.

The maximum number of transition data transmitted to the DataIn port during each calculation step is set to 250 in the current implementation. This is the total number of transitions that can be specified in the model for the group of 8 channels connected to that DataIn port.The actual number of transitions per digital output channel is fixed by the 'Number of events per channel' parameter.

Parameters

ControllerName	Bind this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block The OpCtrl block controls initialization of the settings of one specific FPGA in the system.
DataIn port number	Enter the number of the DataIn port to be controlled by this block, in the range [1:64] for the VC707, TE0741 and OP48xx FPGAs and [1:32] for all others.
Slot infos	This non-editable parameter displays the physical location of the digital output channels related to the selected port, as obtained from the parsing of the configuration file.
Maximum number of channels controlled by this block	This non-editable parameter displays the number of channels in one sub-section listed in the configuration file, typically 8.
Number of channels	Enter the number of channels for which data values will be transmitted at each calculation step. This number must be less than or equal to the value of the 'Maximum number of channels' parameter. The data transfer mechanism between RT-LAB and the FPGA does not allow the selection of individual channels in the sub-section of channels. The transition information supplied by the block will thus apply to the N first channels of the sub-section, where N is the value of the 'Number of channels' parameter.
Number of events per channel	This parameter controls the amount of transition data for each digital output channel transferred from the RT-LAB model to the FPGA at each calculation step. If the value entered is a single integer value, it applies to all channels. The value can also be entered as a vector of values, each element of the vector specifying the number of events for one channel. This parameter is used to set the widths of the States and Times outputs.
Time unit	Select the time unit of the Times input values. If 'Time ratio' is selected, the Times values represent the ratio of the transition time relative to the beginning of the calculation step, over the duration of the step. If 'Seconds' is selected, the Time values represent the delay between the beginning of the calculation step and the time of the occurrence of the transition.

Inputs

This block has two inputs, States and Times, for each channel in the subset of digital output channels selected.

Times Inputs values must be supplied in chronological order, i.e. the first value of each States and Times vectors corresponds to the first transition to occur on the digital output channel during the next calculation step, the second value to the second transition etc.

The values must be supplied as follows:

States:

Possible Values	Description
1	Rising edge transition requested
0	Falling edge transition requested
-1	No transition

Times:

Possible Values (time ratio)	Description
0 <= x < 1	Ratio of the time of occurence of the transition (Ttr) over the duration of the calculation step (Ts). Ttr is the time offset of the transtion relative to the beginning of the calculation step where the transition is to occur : Ttr = [0:Ts]; and x = Ttr / Ts
1	No transition
Possible Values (seconds)	Description
0 <= x < Ts	Desired time delay between beginning of calculation step and occurrence of transition
Ts	No transition

Outputs

Status: This output returns the following values:

Value	Description
0	No error.
-1	Block could not be matched with an OpCtrl block (check the 'controller Name' value), or FPGA initialization problem.
-2	Internal memory initialization problem.

Characteristics and Limitations

PWM Processing

When Event Generator block is used to generate PWM signal, processing time increases with the number of events to compute so its increases with the PWM frequency and the number of channels. The amount of data transferred between the FPGA and CPU also increases with the number of events since that the transition times must be transferred for each step.

Connector Pin Assignments

Direct Feedthrough	No
Discrete sample time	Inherited
XHP support	Yes
Work offline	No

RT-LAB Documentation

Common Event Generator