Block

Mask

Description

The block LoadOut is used to read registers of Opal-RT card. The access to FPGA register is used to retrieve specific data from FPGA. It takes more time than DataOut Recv and should be used ponctually.

One LoadOut block controls data reception from one of the LoadOut ports of the bitstream programmed in the card. The bitstream must be produced with Opal-RT RT-XSG product, version 2.0 or higher.

In the RT-XSG implementation, the bitstreams can have at least 32 LoadIn input ports and 32 LoadOut output ports. On VC707 and TE0741 FPGA based platforms, the bitstreams can have up to 64 LoadIn input ports and 64 LoadOut output ports if the RT-XSG revision used to generate the bitstream is 3.3.4 or above. Each port has a maximum width of 250 32-bit data words. These data ports are used to exchange data between the RT-LAB model and the FPGA chip of the card via the PCIe bus of the target computer.

Parameters

ControllerName	Bind this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block The OpCtrl block controls initialization of the settings of one specific card in the system.
LoadOut port number	Enter the number of the LoadOut port to be controlled by this block, in the range [1:64] for VC707 and TE0741 FPGAs or [1:32] for all others.
LoadOut port width	Enter the maximum number of data words that will be received from the card at each calculation step, in the range [1:250].
LoadOut port type	Select the data outport type : 'uint32' or 'double'. When 'double' is selected, the underlying driver performs data typecast between 'double' and 'uint32', so data values are limited to the range [0:2^32-1]. The possibility to set the outport to 'uint32' type is provided for optimum performances
Sample Time (s)	This parameter allows the user to specify the block sample time in seconds. The default value is 0, which specifies a continuous sample time (note that the sample time is borrowed from the separated subsystem) while -1 specifies an inherited sample time. The LoadOut block and its associated OpCtrl block must execute at the same sample time.

Inputs

The block has one inport.

Enable: This input is used to trigger data reading from FPGA card. When this input is set to 1, 'Data' outport will be updated with data from FPGA registers.

Outputs

The block has two outports.

Data: The data values returned by this outport are read from FPGA registers when "Enable" is set. No scaling or formatting of the data is performed, except for typecast from 'uint32' to 'double' if the 'Data outport type' parameter is set to 'double'.

Status: The Status output returns the following values:

Value	Description
0	No error.
-1	Block could not be matched with an OpCtrl block (check the 'controller Name' value), card initialization problem.
-2	Data reception timeout. This error can be caused by model synchronization errors.

Characteristics and Limitations

This block has no special characteristics.

Direct Feedthrough	No
Discrete sample time	Yes
XHP support	Yes
Work offline	No

RT-LAB Documentation

Common LoadOut