Block

Mask

Description

The PWM Out block is used to produce PWM signals on the digital output lines of a carrier connected to an FPGA.

Two inputs are used to generate PWM signal: the carrier frequency and the duty cycle. These values are transferred to the FPGA bitstream from the RT-LAB model through one DataIn port of the bitstream, via the PCIe bus of the target computer.

The shape of PWM signals is defined by the polarity, the dead time between complementary signals, the initial phase. These parameters do not need to be sent at each step so the LoadIn port assigned to PWMO is used to transfer them to the FPGA.

Each FPGA bitstream using digital output channels in PWM Out mode comes with a configuration file which lists the LoadIn port, the DataIn port number and its corresponding carrier location in the system. The configuration file name is the same as the bitstream file name entered in the OpCtrl block, with the extension .conf instead of .bin.

This configuration file uses three parameters to describe the selection of the carrier channels:

the Slot number (in the range 1 to 4) is the slot of the backplane connected to the system in which the Digital Output module is installed,
the Section A or B is a subset of 32 lines of the carrier. For example, with the 32 In/32Out OP4510 carrier, section A refers to the 32 input lines and section B to the 32 output lines,
the Sub-Section, 1 to 4, is a subset of 8 data values connected to the port: subset 1 returns values for the 8 first channels of one section of the carrier, subset 2 returns values for the 8 next channels, etc.

The user must refer to the configuration file for selecting the port number for the desired digital output channels. The PWM Out block then parses the configuration file and displays the Slot, Section and Sub-section values corresponding to the port number in the 'Slot infos' parameter. During the parsing of the configuration file, the block retrieves also the matching LoadIn port.

The maximum number of digital output channels controlled by one PWM Out is limited by the size of the subset of channels in one sub-section, which is fixed to 8 in the current implementation.

Parameters

ControllerName	Bind this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block The OpCtrl block controls initialization of the settings of one specific FPGA in the system.
DataIn port number	Enter the index of the DataIn port to be controlled by this block, in the range [1:64] for the VC707 and TE0741 FPGAs and [1:32] for all others.
Slot infos	This non-editable parameter displays the physical location of the digital output channels related to the selected DataIn port, as obtained from the parsing of the configuration file.
Maximum number of PWM signals controlled by this block	This non-editable parameter displays the number of channels in one sub-section listed in the configuration file.
Number of PWM signals	Enter the number of independent PWM signals, or the number of pairs of complementary PWM signals, which will output from the specified digital module. The value of the number of signals must be less than or equal to the value of the 'Maximum number of PWM generators' parameter. This number always equals to the length of the two vectors for the input of this block (Hz and Duty cycle, see the Inputs Section below for more details). The data supplied by the block will thus apply to the N first channels of the sub-section, where N is the value of the 'Number of PWMOut channels' parameter. When 'Complementary mode was selected, the maximum number is divided by 2. In the 'Complementary Mode', the complementary signal is generated on the next PWM channel as shown in Figure 2: Complementary Waveform.
Polarity	This parameter is used to specify the PWM signal polarity. The polarity can be either Active-High (default) or Active-Low. ‘Active-Low’ means that a ‘Low’ output voltage is interpreted as a ‘1’ and a ‘High’ input voltage is interpreted as a ‘0’. ‘Active-High’ for this parameter means that the signal is active-high (default), which means that a ‘Low’ input voltage is interpreted as a ‘0’ and a ‘High’ input voltage is interpreted as a ‘1’. In 'Complementary Mode', when a 'Deadtime value' is set and 'Polarity' is 'Active Low', the PWM signal is set to '1' during the delay specified by the 'Dead Time value' parameter;when 'Polarity' is 'Active High', the PWM signal is set to '0'.
Carrier wave mode	This parameter sets the PWM generation pattern. If the generation mode is set to ‘Symmetric’, the PWM carrier is a triangular waveform. An ‘Asymmetric’ generation mode corresponds to a sawtoothed carrier waveform. As a result, the symmetric PWM active phase is symmetric to the beginning of the PWM period while the asymmetric PWM active phase is asymmetric to the beginning of the PWM period.
Carrier phase control from an input	When selected, an extra input Phase is added to the block (refer to section Inputs) to allow the update of initial phase in real time.
Dead-time control from an input	When selected, an extra input Dead time is added to the block (refer to section Inputs) to allow the update of dead time in real time. Note that this option is available when Output complementary channel is set.
Allow disabling channel	When selected, an extra input Disable is added to the block (refer to section Inputs), to allow disabling channels in real time. If Output complementary channel is set, an element of this input array will control both the channel and its complementary output. The duty cycle of both physical channels (the PWM generator and its complementary) will be set according to the polarity chosen (i.e. 0 for active high polarity and 1 for active low polarity).
Output complementary channel	When selected, the PWM block generates the complementary signal and the number of PWM channels is divided per 2. The other channels are used to generate the complementary PWM signal according to Figure 2 below.
Dead time value (seconds)	This parameter is available only if a complementary waveform is requested. It corresponds of the duration of this dead time, in seconds. Note that the inclusion of a dead time will reduce the length of the active phase of the two complementary waveforms, thus reducing the duty cycle. This value is in seconds. When 'Polarity' is 'Active Low', the PWM signal is set to '1' during the delay specified by the 'Dead Time value' parameter and if 'Polarity' is 'Active High', the PWM signal is set to '0'. The dead time range is [0.01 10,23] us.
Initial phase [0..1]	This parameter is used to specify the phase between each PWM signal and the carrier wave. Then, it is a vector (1 x n) where n is the number of PWM signals generated. The initial phase of the carrier is expressed as a cycle ratio, between 0 and 1. It is quantized to the nearest 1/1000.

Inputs

Hz	This input sets the PWM carrier frequency. The value should be provided in Hz; it should be between 0 and 180,000 Hz for bitstreams generated with RT-XSG version up to v3.3.3. After this version, the limit for the maximum frequency will depend on the hardware used in the system.
Duty	This input is the duty cycle. Its should be inside the [0,1] range. When the value is out of range, the duty cycle is saturated.
Dead time	This input is available only if a complementary waveform is requested and the Dead-time control from an input is set. It is equivalent to the Dead time value parameter for real time. The value should be provided in seconds. The dead time range is [0.01 10,23] us.
Phase	This input is available if Carrier phase control from an input is set. It is used to specify the phase between each PWM signal and the carrier wave. Its should be inside the [0,1] range. When the value is out of range, the phase cycle is saturated.
Disable	This input is available if Allow disabling channel is set. It is used to disable channels in real time. The input is an array with the size mentioned in Number of PWM signals. If Output complementary channel is set, an element of this array will control both the channel and its complementary output. The duty cycle of both physical channels (the PWM generator and its complementary) will be set according to the polarity chosen (i.e. 0 for active high polarity and 1 for active low polarity).

Outputs

The Status output returns the following values:

Value	Description
0	No error.
-1	Block could not be matched with an OpCtrl block (check the 'controller Name' value), or FPGA card initialization problem.
-2	Internal memory initialization problem.

Characteristics and Limitations

Direct Feedthrough	No
Discrete sample time	Inherited
XHP support	Yes
Work offline	No

RT-LAB Documentation

Common PWM Out