Block

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Table of Contents

• 1 Block
• 2 Description
• 3 Mask Parameters
• 4 Inputs
• 5 Outputs

Description

This block is a feature template for users to define their own custom RT-XSG designs. The block offers a connection interface to connect to and from eHS as well as to and from the CPU. The custom model will be added to the .ioconf making it possible to connect it to a .ehs Schematic Editor model to use with eHS. The block also has a CPU block to send values to the FPGA from the CPU and from the FPGA to the CPU.

Mask Parameters

Open

Open Custom Model Design (button): This button navigates to the model space where the user can define his custom model design.

Input Bus (checkbox): This option allows to add a “Input Bus” port to the block. The input bus port is meant to be used as a general purpose port where the user can input any signals from the rest of the firmware model.

Output Bus (checkbox): This option allows to add a “Output Bus” port to the block. The output bus port is meant to be used as a general purpose port where the user can output any signals to the rest of the firmware model.

-eHS Interfaces Tab-

eHS Inputs (checkbox): This option allows to define signals coming from eHS to be mapped to the custom model. The signal format is XFLOAT_42_34. Unchecking the checkbox removes the associated ports from the block.

Unpack FLWS signals to parallel (checkbox): This option defines whether the signals coming from eHS should be unpacked or kept as a FLWS bus.

eHS Outputs (checkbox): This option allows to define signals coming from the custom model to be mapped to eHS. The signal format is XFLOAT_42_34. Unchecking the checkbox removes the associated ports from the block.

Pack parallel signals to FLWS (checkbox): This option defines whether the signals coming from the custom model should be packed to FLWS as a parallel bus.

-CPU Interfaces Tab-

CPU Inputs (checkbox): This option allows to define signals coming from the CPU to be mapped to the custom model. The signal format is UFIX_32_0. Unchecking the checkbox removes the associated ports from the block.

CPU Outputs (checkbox): This option allows to define signals coming from the custom model to be mapped to the CPU. The signal format is UFIX_32_0. Unchecking the checkbox removes the associated ports from the block.

Inputs & Outputs (textbox): Define your signals in the textboxes separated by a newline.

Inputs

from eHS low latency: This input should be connected to the low latency port of eHS. It receives all the low latency measurements of eHS and maps inside the block only the ones defined in eHS Inputs.

LoadIn and LoadIn SOF: This input should be connected to a LoadIn port from the LoadIn block. The loadIn data is being automatically generated from the Schematic Editor’s external model connections.

Data and DataIn SOF: This input should be connected to a DataIn port from the DataIn block. The DataIn data is being automatically generated from the CPU model Custom Model CPU block.

Outputs

to eHS: This output port provides FLWS bus to connect to a FLWS input of eHS.

to DataOut: This output port should be connected to a DataOut port of the DataOut block. It sends the defined CPU Outputs to the CPU model.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/ .