Description

This block provides a generic Parallel to Parallel interface. It allows the user to route inputs to outputs programmatically using a user-defined configuration stream.

Functionality is triggered by a Sync signal. When triggered it takes a maximum of Number of inputs clock cycles to update the outputs.

Mask Parameters

Number of output signals: This parameter defines the number of outputs.

Number of input signals [Read Only]: This parameter defines the number of inputs.

Block Identifier [Read Only]: This parameter defines the internal OPAL-RT block identifier.

User Block Identifier: This parameter defines the user block identifier. This allows to connect several blocks to the same LoadIn.

FPGA period: This parameter is used when running offline simulation (Advanced Users). It defines the hardware period of the FPGA. Default is 5ns for 200MHz clock.

Inputs

Config

LoadIn: This input should be connected to a LoadIn port. It receives the user-defined configuration fromt the RT-LAB model.

LoadInSof: This input should be connected to a LoadIn SOF port. Port number must be the same as LoadIn one.

Data

ParrallelIn: This input should be connected to a Simulink bus signal which size is equal to Number of inputs. Data types of each signal of the bus has to be the same

Sync: This input is active high. When active, it triggers the writting of outputs using user-defined configuration.

Rst

Rst: This input is used as a active high global reset for the functionality. When used, user-configuration needs to be sent again, and data is equal to 0.

Outputs

Out: This output provides a Simulink bus which size is equal to the number of outputs parameter.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.