Timing Diagrams

At each clock cycle, if the Valid signal is true, the Data is latched. Otherwise, the Data signal is not taken into account. The Data bits could be sent consecutively or with gaps between valid frames. For example, in the figure above, there is a gap between valid Data 1 and valid Data 2, but no gap between valid Data 2 and valid Data 3. The Last data bit must be activated at the end of a complete set of frames. In order to optimize latency, it is recommended to activate the Last bit in the same clock cycle as the last valid frame is sent, but it is acceptable to activate it between the final valid frame of the previous set and the valid frame of the next set.

Library Blocks

RAW vs BUS
The term Raw is used to indicate that Data are packed together as unsigned bits. For instance a XFloat_8_34 using a FLWS RAW protocol will be modeled as a UFIX_44_0. Alternatively, the term Bus refers to the use of Simulink Bus Creators, with the following bus signal names: Data / Valid / Last.

FLWS_Raw_Unpack: Unpack a FLWS RAW input signal into a Data / Valid / Last signals.

FLWS_Raw_Pack: Pack Data / Valid / Last signals into FLWS RAW ouput signal.

FLWS_RawToBus: Converts a FLWS Raw to a FLWS Bus signal.

FLWS_Bus_Unpack: Unpack a FLWS Bus input signal into a Data / Valid / Last signals.

FLWS_Bus_Pack: Pack Data / Valid / Last signals into FLWS Bus ouput signal.

FLWS_BusToRaw: Converts a FLWS Bus to a FLWS Raw signal.

FLWS_Bus_Dummy: Outputs a dummy (Data / Valid / Last are null) FLWS Bus signal.

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