Description

This block allows to monitor up to 8 signals from up to 4 different channels. The sampling rate varies between 5 ns and 20 µs. The selected signals and the sampling rate can be chosen dynamically, and will be available for monitoring in the RT-LAB model. It must be controlled from the RT-LAB model.

The selected signals are stored in a RAM buffer allowing an asynchronous monitoring in RT-Lab model. The size of the buffer varies from 1k samples to 32k samples, and must be chosen before compiling the bitstream.

Mask Parameters

Basic Parameters Tab

Number of serial inputs: This list allows to choose the number of required serial input. Minimum is 1, and maximum is 4.

Number of channels: This list allows to choose the number of channels that will be monitored in RT-LAB. Minimum is 1, and maximum is 8.

Number of samples: This list allows to choose the number of samples that will be stored for each channels. Minimum is 1k, and maximum is 32k.

Number of RAM blocks required: This gives the user information of how many RAM blocks are required for the implementation of the RT-XSG Scope Series. When FPGA resources are scarce, limiting the number of channels, the number of samples, or the internal data size (from Advance Parameters tab) can help reduce the number of RAM blocks required, easing the bitstream compilation.

Advanced Parameters Tab

Internal Data Size Choosing 32 bits gives access to the full range of the SFP, removing a few lower bit of the fraction reduces the precision of the number but it is not noticeable with the naked eye.

Internal Data Address Size: This option is not available to be changed at this time. Using a value of 7 allows to address up to 128 signals from each serial input.

FPGA period: This value should be set to the sampling rate of the FPGA design.

Inputs

LoadIn & LoadInSof: This input should be connected to a LoadIn block from which configuration of the RT-XSG Scope Series is sent from the RT-Lab model.

Serial In 1-4: This input should be connected to a serial output which follows the FLWS standard, such an eHSx128Gen3s or Serializer.

MdlSynch: This input should be connected to the signal ModelSync from the design.

Rst: This input should be connected to a reset signals from the design. We recommend using the Reset from the eHSx128Gen3s.

Outputs

Scope Data: This output is used for communication from the RT-XSG Scope block and the controller located in the RT-LAB model through a DataOut port. It must be connected to the DataOut block, which must be configured in FIFO.

Characteristics and limitations

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.