Description

This block implements an interconnect function enabling mapping between input signals and outpout signals to be modified on-the-fly during model execution.

The mapping is applied in real time from the RT-LAB model, assigning output channels to any of the signals made available by this block.

Mask Parameters

Output signal format: This parameter sets the output format of all outputs. Input format of the signals selected in this block should match this type.

Available signals in input bus: This signal list is generated automatically with the complete list of signals provided in the "Model Signal Bus" composite input. It is not editable from this block parameter panel, as names are inherited from the names of the nets composing the input bus. Signals available for output interconnection mapping must be selected from this list.

Selected signals available for output interconnection mapping: This parameter lists the signals that will be available for mapping to this block outputs during the real-time simulation. These signals must be selected from the "Available signals in input bus" through the "Add >>" button. Each signal is attributed an index, and the control block in the RT-LAB model will refer to this index in order to map the output interconnection information. Indices can be changed through the "Up" and "Down" buttons, or a signal can be removed from the selection through the "Remove" button.

Inputs

Sel: This input should be a bus containing all the interconnection information. It should be connected to a "FPGA 64-to-64 Interconnect Unpacking" block.

Input Signals: This input should be connected to a composite net listing all the signals that the developer wants available for the interconnection module. All signals should be named properly, and the signals intended to be made available to the block outputs should have the signal type set in this block corresponding mask parameter..

Trig: When active, this input trigs the acquisition of the inputs and starts the output mapping. It should be a Bool or UFix1_0 pulse train of period equal to at least 20 FPGA clock cycles.

Outputs

Output Signals: These outputs are the 64 output channels of the interconnection block.

Characteristics and limitations

The use of this block is limited to 64 signals made available to be assigned to the output signals.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.