Description

Opal-RT Generic Machines - This block allows to simulate up to 4 machines with their mechanical model, resolver, and encoder. The following machines are supported, and can be configured from the CPU model.

• Squirrel Cage Induction Machine (SCIM)
• Double-Squirel Cage Induction Machine (DSCIM)
• Doubly Fed Induction Machine (DFIM)
• Synchronous Machine with Salient Rotor Pole
• Synchronous Machine with Round Rotor Pole

Mask Parameters

The Number of Generic Machines parameter is used to choose between the support of four or two machines in the XSG block. By default, the option is set to Quad and Dual is primarily used for smaller FPGAs because of it's smaller footprint

Inputs

eHS_FLWS: Frame-based Lightweight Serial Protocol (FLWS) port which allows to receive data from the eHS.
There are three (3) signals in the bus:

• Data. Data type is XFloat_8_34.
• Valid. Data type is UFix_1_0.
• Last. Data type is UFix_1_0.

AnalogIn_FLWS: Frame-based Lightweight Serial Protocol (FLWS) bus port which allows to send analog input to the resolvers part of the model.
There are three (3) signals in the bus:

• Data. Data type is XFloat_8_24.
• Valid. Data type is UFix_1_0.
• Last. Data type is UFix_1_0.

DataIn: This port allows to send data (one soft reset, and then torque load, enable mechanical model, and speed for all four motors) to the mechanical model. Port data type is UFix_33_0.

DataIn_SOF: This port is the Start of Frame signal of the DataIn port. Port data type is UFix_1_0.

LoadIn: This port allows the configuration of the block when using a specific configuration structure. The LoadIn signal should be connected to a RT-XSG LoadIn port. Port data type is UFix_33_0.

LoadIn_SOF: This port is the Start of Frame signal of the RT-XSG LoadIn port. Port data type is UFix_1_0.

Reset: This port clears the motor configuration and state-variables.

Outputs

DataOut: Output UFix_33_0 which should be connected to a DataOut block, configured to received data asynchronously. Depending on the number of machine used, between 1 to 4, 24 to 96 measurement will be sent to the CPU. The bit 33 is the valid signal, and the 32 lsb are a XFloat_8_24 .
The measurement are sent as follow:

1. Vsq, Quadratic stator voltage.
2. Vsd, Direct stator voltage.
3. Vrq, Quadratic rotor voltage.
4. Vrd, Direct rotor voltage.
5. Phisq, Quadratic stator flux.
6. Phisd, Direct stator flux.
7. Phirq, Quadratic rotor flux.
8. Phird, Direct rotor flux.
9. Isq, Quadratic stator current.
10. Isd, Direct stator current.
11. Irq, Quadratic rotor current.
12. Ird, Direct rotor current.
13. isa, First stator phase current.
14. isb, Second stator phase current.
15. isc, Third stator phase current.
16. ira, First rotor phase current.
17. irb, Second rotor phase current.
18. irc, Third rotor phase current.
19. Torque, Electrical torque.
20. w, Motor speed in rad/s.
21. thetam, Mechanical rotor angle in rad.
22. Resolver sin, sin waveform from the resolver.
23. Resolver cos, cos waveform from the resolver.
24. Resolver carrier, carrier waveform from the resolver.

Note that for the synchronous machine, field current is mapped to ira, where irb, and irc should be ignored.

eHS_Feedback_FLWS: Frame-based Lightweight Serial Protocol (FLWS) bus port which allows to send feedback currents from the generic machine core. The FLWS bus will have between 6 and 24 data depending the number of machines used.
There are three (3) signals in the bus:

• Data. Data type is XFloat_8_34.
• Valid. Data type is UFix_1_0.
• Last. Data type is UFix_1_0.

The measurement are sent as follow, then it is repeated for the second, third, and fourth machine:

1. isa, first phase current on stator.
2. isb, second phase current on stator.
3. isc, third phase current on stator.
4. ira, first phase current on rotor.
5. irb, second phase current on rotor.
6. irc, third phase current on rotor.

AnalogOut_FLWS: Frame-based Lightweight Serial Protocol (FLWS) bus port which allows to send analog output. Has the same structure and contains the same data as DataOut but is triggered automatically by an internal logic.

Encoders: Output bus containing the variables from the four encoders.
The variables are the following, and are repeated for each encoder (1, 2, 3, 4):

• A, A signal. Data type is UFix_1_0.
• B, B signal. Data type is UFix_1_0.
• Z, Z signal. Data type is UFix_1_0.

Characteristics and limitations

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.