Description

This block decodes the initialization stream by separating it in five disctinct signals (Data, Valid, ParamID, Addr, DataID and Reset) only if the block ID input is the same as the one defined in the block.

Mask Parameters

FPGA period: This parameter sets the internal counter period value.

Block ID: This parameter sets the block ID value. Set this parameter to the value of block ID in which the initialization decoder will be added.

Inputs

Reset: This input provides a manual reset signal port.

Init_bus: The LoadIn initialization signal should be connected to this port.

Ibit_bus_sof: The LoadIn start of frame (sof) signal should be connected to this port.

Block Index: This input sets the block index value. Set this input to the value of block index of the block (typically 0).

Outputs

Init_data: The restructured initialization signal is outputted through this port. It has the following form: Data, Valid, ParamID, Addr, DataID and Reset.

Characteristics and limitations

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