Description

This block contains the eHS Gen5 Solver core, a powerful floating-point solver, which enables the user to simulate a power electronics circuit on FPGA automatically without having to program the mathematical equations. This block solves the current and voltages within the circuit on an Opal-RT FPGA based simulator with sample times below 1µs.

Mask Parameters

Number of gating inputs: This option allows to use up to 8 gating inputs to connect the eHS to external gates.

Is gating input (1 to 8) oversampled: Defines whether or not the selected gating input is oversampled (UFix160_0) or not (UFix32_0). If it isn't already oversampled (UFix32_0) the block will automatically oversample the data to 160 bits under the mask.

Number of FLWS inputs: This option allows to use up to 6 FLWS inputs to connect the eHS to external sources or models.

Inputs

From CPU: This input should be connected to the DataIN and LoadIN blocks through an eHS Gen4 Unpacking block (same unpacking for Gen4 and Gen5) . It receives all necessary info from the RT-LAB model.

Gating input (1 to 8): If this option is selected in the CPU block, this port enables the use of explicit gating signals coming from digital inputs by eHS. The effective number of bits of this input depends upon the solver form factor. Consult the table below for the expected data types depending on the solver form-factor.

FLWS input (1 to 6): If this option is selected in the CPU block, this port enables the use of an output originating from another eHS core to control a current or voltage source within the solver. This signal should follow the OPAL-RT FLWS protocol.

Outputs

Outputs : This output port provides FLWS bus that streams the eHS outputs for use in the RT-XSG model. It is provided as a Bus following the OPAL-RT FLWS protocol.

Low latency outputs: This output port provides a FLWS bus that streams the eHS low latency outputs. The low latency outputs of the eHS are provided to couple external models in order to optimize the coupling latency and enhance the stability of the model decoupling.

GatePeriodMonitoring: Monitoring signal for gate period. Mainly used for debugging purposes.

GateTimeOnMonitoring: Monitoring signal for gate time on. Mainly used for debugging purposes.

DataOut Averaged: Averaged outputs sent to DataOut to CPU simulation.

DataOut Downsampled: Downsampled outputs sent to DataOut to CPU simulation.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.