Description

This block implements sixteen (16) capacitor differential equations. The FPGA resources used for the computation of the solution of these differential equations is shared between all sixteen capacitors.

Mask

Inputs

reset: This input must be a Bool signal. When active, the voltage across the capacitors is reset to their initial value.

Trigger: This input must be a Bool signal. It should be a pulse train whose period is equal to the sample time provided in the corresponding CPU block parameter panel.

Ic: This input is a vector of Single-precision signals (Xfloat8_24). The capacitor current, used to compute the voltage across them, is chosed from this vector, which must have sixteen elements.

C solver parameters: This input should be a bus containing all the solver paramet6ers. It should be connected to a "Time-multiplexed Capacitor Differential Equation Solver Unpacking" block.

Outputs

Vc: This output is a vector, each element being the voltage computed across a capacitor, in a single floating point format (Xfloat8_24).

Characteristics and limitations

The differential equation is solved using the backward-Euler integration technique, that is Vc(n) = Vc(n-1)+Ic(n-1)*Ts/C.

Sample time: The block minimum sample time is 85 ns. The computation total latency is 180 ns.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.