Description

This block provides a way to change values sent to the FPGA during the execution of the simulation.

With the VDQ model, this block allows the user to:

• Update Ra, Rb and Rc values
• Force Ld and Lq values
• Force Id and Iq values at the table Input
• Force the theta angle to a position
• Update the cut-off frequency of the Vabc monitoring filter
• Force the flux value

The purpose of this block is to concatenate the values in a standard bus signal which can be read by advanced command capable blocks such as the PMSM VDQ model block.

Inputs

Inputs of this block should always be constants block.

Using the RT-LAB variable monitor, it is possible to change the values send to the FPGA by changing the constants values.

Outputs

The output must be connected to an advanced command capable block port.

An example is the PMSM VDQ model block.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.