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Selectable Digital Input - efs_cpuSelectableDI
Description
This block implements an 8-channel digital input subsection as either Static digital intput, EventDetector input or Pulse-Width Modulated input.
Mask Parameters
Controller Name:Bind this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block The OpCtrl block controls initialization of the settings of one specific FPGA in the system.
DataOut port number: Enter the number of the DataOut port to be controlled by this block, in the range [1:32].
LoadIn port number for Digital Input type selection: Enter the number of the LoadIn port used to communicate the Digital Input type selection for this block, in the range [1:32].
Digital Input type: Select the Digital Input type from the list. This type can either be "Static Digital Input", "Event Detector" or "Pulse-Width Modulated Input".
Other parameters will appear depending on the Digital Input type selection. More information on these parameters can be found in the block documentation of either digital input type.
Inputs
Inputs of this block are Digital-Input-type dependent. Refer to the block documentation of either digital input type for more information.
Outputs
Outputs of this block are Digital-Input-type dependent. Refer to the block documentation of either digital input type for more information.
Characteristics and limitations
The block documentation of either digital input type can be accessed here: Static Digital Input, Event Detector, Pulse-Width Modulated Input,
Direct Feedthrough | NO |
Discrete sample time | YES |
XHP support | YES |
Work offline | N/A |
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