Description

This block implements a signal mapping and rescaling interface to control analog output channels according to signals originating from the RT-XSG or RT-LAB model. It must be controlled from the RT-LAB model.

The mapping is applied in real time from the RT-LAB model, assigning channels from signals made available by this block.

Mask Parameters

Block ID: This parameter was used to set up the block ID but now discarded.

Available signals in input bus: This signal list is generated automatically with the complete list of signals provided in the "Model Signal Bus" composite input. It is not editable from this block parameter panel, as names are inherited from the names of the nets composing the input bus. Signals available for analog output mapping must be selected from this list.

Selected signals available for analog output mapping: This parameter lists the signals that will be available for mapping to analog outputs during the real-time simulation. These signals must be selected from the "Available signals in input bus" through the "Add >>" button. Each signal is attributed an index, and the control block in the RT-LAB model will refer to this index in order to map the signal to an analog output channel. Indices can be changed through the "Up" and "Down" buttons, or a signal can be removed from the selection through the "Remove" button.

Inputs

Sync_AOut: This input must be a Bool or UFix1_0 signal. It should be a pulse train whose period is equal to the sample time requested for the Analog Output channels. Refer to the Hardware documentation for the minimum sampling time of the interface.

Model Signal Bus: This input should be connected to a composite net listing all the signals that the developer wants available for the analog output module. All signals should be named properly, and in Single Floating-Point format (XFloat8_24).

Model Signal Serial: This input has to follow the OPAL-RT FLWS Protocol. Inner data size is 32 bits (i.e XFloat8_24), any additional bit would be discarded. As an example this signal could be provided by the newer eHS solver generations (Gen3s onwards).

Configuration: This input should be a bus containing all the solver parameters. It should be connected to a "Analog Output Mapping and Rescaling Unpacking" block.

Rst: This input must be a Bool signal. When put active, the voltage of the analog output will go to 0V at the next synchronization pulse.

Outputs

Conv1: This output is conversion command that should be connected to the first Analog Output I/O interface.

ch{0..15}: These outputs are the 16 mapped and rescaled channels that should be connected to the first Analog Output I/O interface.

Conv2: This output is conversion command that should be connected to the second Analog Output I/O interface.

ch{16..31}: These outputs are the 16 mapped and rescaled channels that should be connected to the second Analog Output I/O interface.

Characteristics and limitations

The use of this block is limited to analog output interfaces that accept the UFix16_11 fixed-point format for their inputs.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.