Description

This block is used to measure the minimum and the maximum on the FPGA target. This block receives serial inputs representing the measurements received from the eHS core.

Inputs

SerialInput: This input is a bus representing signals to measure. The number of valid consecutive frames between End of Frame (EOF) signals being '1' must not exceed 128. The frames expected must follow the standard described below.

The size of each frame is 34 bits and the data type is of UFix_34_0, with the following sections:

• Data : 32 bits for the data
• Valid: 1 bit describing if the data in the frame is valid
• Eof : 1 bit representing the last valid data point in the frame

Reset Window: This signal must connect to a pulse generator. It used to reset the measurement of the minimum and the maximum. At each time the Reset Window input is set to '1' the measurement of the minimum and the maximum will be reset.

Outputs

Serial Min Output: This output is almost the same data type and serial format as the SerialInput input, namely of UFix34_0 format where the first 32 bits represent the data, bit 33 is the valid signal, and bit 34 (MSB) is the end of frame signal. The data represent the minimum of the signal set in SerialInput.

Serial Max Output: This output is almost the same data type and serial format as the SerialInput input, namely of UFix34_0 format where the first 32 bits represent the data, bit 33 is the valid signal, and bit 34 (MSB) is the end of frame signal. The data represent the minimum of the signal set in SerialInput.

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