Block

Mask

Description

The Pulse-Width Modulated Digital Output block is used to generate PWM signals according to specific or variable duty cycle or carrier frequency. The user can specify the polarity of the signal and generate a complementary waveform. When a complementary waveform is requested, a dead time between the phases can be applied. Either symmetric or asymmetric generation patterns can be selected by the user, and phase synchronization can be managed by an external signal.

Parameters

Signal polarity	Used to specify the input signal polarity. The polarity can be either Active-High (default) or Active-Low. Alternatively, the polarity can be set via an input port. ‘Active-Low’ for this parameter means that the signal is active-low, which means that a ‘Low’ output voltage is interpreted as a ‘1’ and a ‘High’ input voltage is interpreted as a ‘0’. ‘Active-High’ for this parameter means that the signal is active-high (default), which means that a ‘Low’ input voltage is interpreted as a ‘0’ and a ‘High’ input voltage is interpreted as a ‘1’.
Apply carrier frequency	Determines how the PWM carrier frequency is specified. It can be specified either by a block parameter or by a block input port.
Carrier frequency	If the PWM carrier frequency is specified via a block parameter, this entry is made available. It is used to set a constant carrier frequency. The frequency is calculated at the FPGA model compilation.
Generate a complementary waveform	When selected, this option adds an output to the block that corresponds to the complementary PWM waveform.
Apply dead time	This parameter is available only if a complementary waveform is requested. It is used to specify if a dead time between the active phase of the two waveforms should be included. The duration of this dead time may be specified either by a block parameter or by a block input port.
Deadtime interval duration, in seconds	This parameter is available only if a dead time is requested, and if this dead time should be specified as a block parameter. It corresponds to the duration of this dead time, in seconds. Note that the inclusion of dead time will reduce the length of the active phase of the two complementary waveforms, thus reducing the duty cycle.
Add an 'On/Off' input to deactivate outputs temporarily	This option adds a ‘On/Off’ input port. If this input is inactive, the outputs are forced to the inactive state. This input is synchronized with the ‘Sync’ input signal. Output return to their normal behavior if the synchronized ‘On/Off’ input returns to its active state.
Add a 'Fault' input to deactivate outputs permanently	This option adds a ‘Fault’ input port. If this input is active, the block enters in a fault state outputs are forced to their inactive state. The system may go out of a fault state only if the synchronized ‘On/Off’ input is reactivated (‘0’ - ‘1’ sequence). The ‘Fault’ input is not synchronized.
Create an output port for registered Fault signal	This option adds a ‘Fault_logged’ output port. This port registers the ‘Fault’ signal. It is active if the block is in its fault state. This parameter is available only if the ‘Fault’ input port is requested.
Fault signal minimal duration, in seconds	This parameter is available only if the ‘Fault’ input port is requested. It sets a minimum duration to the Fault signal. Pulses shorter than this duration are not considered.
PWM generation mode	This parameter sets the PWM generation pattern. If the generation mode is set to ‘Symmetric’, the PWM carrier is a triangular waveform. An ‘Asymmetric’ generation mode corresponds to a sawtoothed carrier waveform. As a result, the symmetric PWM active phase is symmetric to the beginning of the PWM period while the asymmetric PWM active phase is asymmetric to the beginning of the PWM period. The PWM generation mode can also be specified via a block input port, by setting this parameter to ‘Block input (0: Asymmetric; 1: Symmetric)’.
Update the Duty cycle	This parameter is used to specify if the frequency at which the duty cycle should be updated. By default, the duty cycle is updated only at the beginning of the PWM period, but for a symmetric generation pattern, it can also be updated in the middle of the PWM period (in the middle of the PWM inactive phase in addition to the middle of the active phase). It is used only if the generation mode is symmetric.
PWM Carrier initial phase definition	This option enables the selection of the way used to specify the initial angle of the PWM carrier. The initial angle can be specified either by a block parameter or by an input port.
Initial phase [0..1]	This parameter is available only if the initial phase is to be provided as a block parameter. The initial phase of the carrier is expressed as a cycle ratio, between 0 and 1. It is quantized to the nearest 1/1000.

Inputs

Sync	This signal is the synchronization signal. It is used to reset the carrier waveform generator phase to zero and to synchronize the Polarity, On/Off, Symm_mode and DeadTime inputs. This signal should be 1-bit wide.
RCO	This signal is the duty cycle. Its should be inside the [0,1] range, although no limitation is set for this signal format. As an example, a UFixX_X format suits well the RCO signal (X=10 gives a 0.1% duty cycle precision).
Polarity	This port is available only if the developer has chosen to provide the signal polarity from a block input port. The value entered should be either a ‘0’ or a ‘1’. A ‘0’ for this input means that the signal is active-low, which means that a ‘Low’ output voltage is generated for a ‘1’ and a ‘High’ output voltage is generated for a ‘0’. A ‘1’ for this parameter means that the signal is active-high (default), which means that a ‘Low’ output voltage is generated for a ‘0’ and a ‘High’ output voltage is generated for a ‘1’.
Frequency	This signal sets the PWM carrier frequency and is available only upon request from the block parameter panel. The value should correspond to the proportion of the carrier period that equals one FPGA clock cycle. It is normal for this signal to be very small, and thus to use a very large bit-count numerical format. The recommended format is UFix42_42 for versions before RT-XSG 3.3.4. Starting RT-XSG 3.3.4, the recommended format is Single Floating Point. The difference being that UFix42_42 only allowed frequencies up to 196 kHz, the newer format removes that restriction.
On/Off	This signal is used to deactivate temporarily the PWM outputs and to reset the block Fault state. If this input is inactive, the outputs are forced to the inactive state. This input is synchronized with the ‘Sync’ input signal. Output return to their normal behavior if the synchronized ‘On/Off’ input returns to its active state. If the block is in its Fault state, a rising edge on this signal brings back the block to its normal state. Starting RT-XSG 3.3.4, the On/Off input can be connected directly to the PWM Unpacking block. The RT-LAB PWMO block allows its control.
Fault	If this input is active, the block enters in a fault state outputs are forced to their inactive state. The system may go out of a fault state only if the synchronized ‘On/Off’ input is reactivated (‘0’ - ‘1’ sequence). The ‘Fault’ input is not synchronized.
Symm_mode	This input sets the PWM generation pattern if it is not set by the block parameter panel. This signal is 1-bit wide (‘0’ corresponding to the Asymmetric mode and ‘1’ to the Symmetric mode). If the generation mode is symmetric, the PWM carrier is a triangular waveform. An asymmetric generation mode corresponds to a sawtoothed carrier waveform. As a result, the symmetric PWM active phase is symmetric to the beginning of the PWM period while the asymmetric PWM active phase is asymmetric to the beginning of the PWM period.
DeadTime	This signal sets the dead time between the two complementary phases of the PWM signal, if those phases are requested, and if the dead time set by an input port is requested from the block parameter panel. It corresponds to an integer number of 10-ns clock cycles in the [0, 1023] range. Starting RT-XSG 3.3.4, this feature is avaible during the execution, you can therefore modify in real-time.
InitPhase	This parameter is available only if the initial phase is to be provided as an input port. The initial phase of the carrier is expressed as a cycle ratio, between 0 and 1. It is quantized to the nearest 1/1000. Thus, numerical format UFix10_10 is recommended. Starting RT-XSG 3.3.4, this feature is avaible during the execution, you can therefore modify in real-time. The limitation being that for phase shifts higher than 5% of the duty cycle, you will experience glitches (small peaks in your PWM signal). If you want to avoid those, don't shift your phase for more than 5% of the duty cycle per frame.

Outputs

HSOut	1-bit wide PWM signal.
HSOut_C	1-bit wide PWM complementary phase and is available only upon request from the block parameter panel.
Fault_logged	This port registers the ‘Fault’ signal. It is active if the block is in its fault state, and is available only upon request from the block parameter panel.

Characteristics and Limitations

The Sync signal fed to this block should be sent synchronously with the beginning of a new PWM carrier period, as it resets the carrier generator to its initial phase. As a result, the most convenient way to generate the Sync input is via a Synchronization manager that sets the Sync and Frequency signals. Note that if no Sync signal is received, the PWM generation will continue perpetually, unless a Fault flag is received, and RCO will continue to be updated at each PWM period and/or mid-period.

One-shot PWM generation can be achieved by appropriate use of the On/Off signal. Before RT-XSG 3.3.4, the maximum frequency was 197 kHz. Starting with RT-XSG 3.3.4, the theoretical maximum will be the clock of your FPGA (100 MHz or 200MHz) but in reality will peak much earlier due to the limitations of the mezzanine cards used. The minimal frequency is 9.094947018e-5 Hz for a 200MHz FPGA frequency or 4.547473509e-5 for a 100MHz FPGA frequency. However, if used with the PWMIn block, the minimal frequency is limited to 96 Hz (because of the latter block) as of RT-XSG 3.3.4 .